35 #if defined ( __ICCARM__ ) 36 #pragma system_include 37 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 38 #pragma clang system_header 41 #ifndef __CORE_CM3_H_GENERIC 42 #define __CORE_CM3_H_GENERIC 74 #define __CM3_CMSIS_VERSION_MAIN (0x04U) 75 #define __CM3_CMSIS_VERSION_SUB (0x1EU) 76 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ 77 __CM3_CMSIS_VERSION_SUB ) 79 #define __CORTEX_M (0x03U) 82 #if defined ( __CC_ARM ) 84 #define __INLINE __inline 85 #define __STATIC_INLINE static __inline 87 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 89 #define __INLINE __inline 90 #define __STATIC_INLINE static __inline 92 #elif defined ( __GNUC__ ) 94 #define __INLINE inline 95 #define __STATIC_INLINE static inline 97 #elif defined ( __ICCARM__ ) 99 #define __INLINE inline 100 #define __STATIC_INLINE static inline 102 #elif defined ( __TMS470__ ) 104 #define __STATIC_INLINE static inline 106 #elif defined ( __TASKING__ ) 108 #define __INLINE inline 109 #define __STATIC_INLINE static inline 111 #elif defined ( __CSMC__ ) 114 #define __INLINE inline 115 #define __STATIC_INLINE static inline 118 #error Unknown compiler 124 #define __FPU_USED 0U 126 #if defined ( __CC_ARM ) 127 #if defined __TARGET_FPU_VFP 128 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 131 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 132 #if defined __ARM_PCS_VFP 133 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 136 #elif defined ( __GNUC__ ) 137 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 141 #elif defined ( __ICCARM__ ) 142 #if defined __ARMVFP__ 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 146 #elif defined ( __TMS470__ ) 147 #if defined __TI_VFP_SUPPORT__ 148 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 151 #elif defined ( __TASKING__ ) 152 #if defined __FPU_VFP__ 153 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 156 #elif defined ( __CSMC__ ) 157 #if ( __CSMC__ & 0x400U) 158 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 172 #ifndef __CMSIS_GENERIC 174 #ifndef __CORE_CM3_H_DEPENDANT 175 #define __CORE_CM3_H_DEPENDANT 182 #if defined __CHECK_DEVICE_DEFINES 184 #define __CM3_REV 0x0200U 185 #warning "__CM3_REV not defined in device header file; using default!" 188 #ifndef __MPU_PRESENT 189 #define __MPU_PRESENT 0U 190 #warning "__MPU_PRESENT not defined in device header file; using default!" 193 #ifndef __NVIC_PRIO_BITS 194 #define __NVIC_PRIO_BITS 4U 195 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 198 #ifndef __Vendor_SysTickConfig 199 #define __Vendor_SysTickConfig 0U 200 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 215 #define __I volatile const 218 #define __IO volatile 221 #define __IM volatile const 222 #define __OM volatile 223 #define __IOM volatile 258 uint32_t _reserved0:27;
269 #define APSR_N_Pos 31U 270 #define APSR_N_Msk (1UL << APSR_N_Pos) 272 #define APSR_Z_Pos 30U 273 #define APSR_Z_Msk (1UL << APSR_Z_Pos) 275 #define APSR_C_Pos 29U 276 #define APSR_C_Msk (1UL << APSR_C_Pos) 278 #define APSR_V_Pos 28U 279 #define APSR_V_Msk (1UL << APSR_V_Pos) 281 #define APSR_Q_Pos 27U 282 #define APSR_Q_Msk (1UL << APSR_Q_Pos) 293 uint32_t _reserved0:23;
299 #define IPSR_ISR_Pos 0U 300 #define IPSR_ISR_Msk (0x1FFUL ) 311 uint32_t _reserved0:15;
324 #define xPSR_N_Pos 31U 325 #define xPSR_N_Msk (1UL << xPSR_N_Pos) 327 #define xPSR_Z_Pos 30U 328 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) 330 #define xPSR_C_Pos 29U 331 #define xPSR_C_Msk (1UL << xPSR_C_Pos) 333 #define xPSR_V_Pos 28U 334 #define xPSR_V_Msk (1UL << xPSR_V_Pos) 336 #define xPSR_Q_Pos 27U 337 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) 339 #define xPSR_IT_Pos 25U 340 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) 342 #define xPSR_T_Pos 24U 343 #define xPSR_T_Msk (1UL << xPSR_T_Pos) 345 #define xPSR_ISR_Pos 0U 346 #define xPSR_ISR_Msk (0x1FFUL ) 358 uint32_t _reserved1:30;
364 #define CONTROL_SPSEL_Pos 1U 365 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) 367 #define CONTROL_nPRIV_Pos 0U 368 #define CONTROL_nPRIV_Msk (1UL ) 385 __IOM uint32_t ISER[8U];
386 uint32_t RESERVED0[24U];
387 __IOM uint32_t ICER[8U];
388 uint32_t RSERVED1[24U];
389 __IOM uint32_t ISPR[8U];
390 uint32_t RESERVED2[24U];
391 __IOM uint32_t ICPR[8U];
392 uint32_t RESERVED3[24U];
393 __IOM uint32_t IABR[8U];
394 uint32_t RESERVED4[56U];
395 __IOM uint8_t IP[240U];
396 uint32_t RESERVED5[644U];
401 #define NVIC_STIR_INTID_Pos 0U 402 #define NVIC_STIR_INTID_Msk (0x1FFUL ) 422 __IOM uint32_t AIRCR;
425 __IOM uint8_t SHP[12U];
426 __IOM uint32_t SHCSR;
430 __IOM uint32_t MMFAR;
433 __IM uint32_t PFR[2U];
436 __IM uint32_t MMFR[4U];
437 __IM uint32_t ISAR[5U];
438 uint32_t RESERVED0[5U];
439 __IOM uint32_t CPACR;
443 #define SCB_CPUID_IMPLEMENTER_Pos 24U 444 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) 446 #define SCB_CPUID_VARIANT_Pos 20U 447 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) 449 #define SCB_CPUID_ARCHITECTURE_Pos 16U 450 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) 452 #define SCB_CPUID_PARTNO_Pos 4U 453 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) 455 #define SCB_CPUID_REVISION_Pos 0U 456 #define SCB_CPUID_REVISION_Msk (0xFUL ) 459 #define SCB_ICSR_NMIPENDSET_Pos 31U 460 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) 462 #define SCB_ICSR_PENDSVSET_Pos 28U 463 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) 465 #define SCB_ICSR_PENDSVCLR_Pos 27U 466 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) 468 #define SCB_ICSR_PENDSTSET_Pos 26U 469 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) 471 #define SCB_ICSR_PENDSTCLR_Pos 25U 472 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) 474 #define SCB_ICSR_ISRPREEMPT_Pos 23U 475 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) 477 #define SCB_ICSR_ISRPENDING_Pos 22U 478 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) 480 #define SCB_ICSR_VECTPENDING_Pos 12U 481 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) 483 #define SCB_ICSR_RETTOBASE_Pos 11U 484 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) 486 #define SCB_ICSR_VECTACTIVE_Pos 0U 487 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL ) 490 #if (__CM3_REV < 0x0201U) 491 #define SCB_VTOR_TBLBASE_Pos 29U 492 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) 494 #define SCB_VTOR_TBLOFF_Pos 7U 495 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) 497 #define SCB_VTOR_TBLOFF_Pos 7U 498 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) 502 #define SCB_AIRCR_VECTKEY_Pos 16U 503 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) 505 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U 506 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) 508 #define SCB_AIRCR_ENDIANESS_Pos 15U 509 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) 511 #define SCB_AIRCR_PRIGROUP_Pos 8U 512 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) 514 #define SCB_AIRCR_SYSRESETREQ_Pos 2U 515 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) 517 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U 518 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) 520 #define SCB_AIRCR_VECTRESET_Pos 0U 521 #define SCB_AIRCR_VECTRESET_Msk (1UL ) 524 #define SCB_SCR_SEVONPEND_Pos 4U 525 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) 527 #define SCB_SCR_SLEEPDEEP_Pos 2U 528 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) 530 #define SCB_SCR_SLEEPONEXIT_Pos 1U 531 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) 534 #define SCB_CCR_STKALIGN_Pos 9U 535 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) 537 #define SCB_CCR_BFHFNMIGN_Pos 8U 538 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) 540 #define SCB_CCR_DIV_0_TRP_Pos 4U 541 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) 543 #define SCB_CCR_UNALIGN_TRP_Pos 3U 544 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) 546 #define SCB_CCR_USERSETMPEND_Pos 1U 547 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) 549 #define SCB_CCR_NONBASETHRDENA_Pos 0U 550 #define SCB_CCR_NONBASETHRDENA_Msk (1UL ) 553 #define SCB_SHCSR_USGFAULTENA_Pos 18U 554 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) 556 #define SCB_SHCSR_BUSFAULTENA_Pos 17U 557 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) 559 #define SCB_SHCSR_MEMFAULTENA_Pos 16U 560 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) 562 #define SCB_SHCSR_SVCALLPENDED_Pos 15U 563 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) 565 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U 566 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) 568 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U 569 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) 571 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U 572 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) 574 #define SCB_SHCSR_SYSTICKACT_Pos 11U 575 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) 577 #define SCB_SHCSR_PENDSVACT_Pos 10U 578 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) 580 #define SCB_SHCSR_MONITORACT_Pos 8U 581 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) 583 #define SCB_SHCSR_SVCALLACT_Pos 7U 584 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) 586 #define SCB_SHCSR_USGFAULTACT_Pos 3U 587 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) 589 #define SCB_SHCSR_BUSFAULTACT_Pos 1U 590 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) 592 #define SCB_SHCSR_MEMFAULTACT_Pos 0U 593 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL ) 596 #define SCB_CFSR_USGFAULTSR_Pos 16U 597 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) 599 #define SCB_CFSR_BUSFAULTSR_Pos 8U 600 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) 602 #define SCB_CFSR_MEMFAULTSR_Pos 0U 603 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL ) 606 #define SCB_HFSR_DEBUGEVT_Pos 31U 607 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) 609 #define SCB_HFSR_FORCED_Pos 30U 610 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) 612 #define SCB_HFSR_VECTTBL_Pos 1U 613 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) 616 #define SCB_DFSR_EXTERNAL_Pos 4U 617 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) 619 #define SCB_DFSR_VCATCH_Pos 3U 620 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) 622 #define SCB_DFSR_DWTTRAP_Pos 2U 623 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) 625 #define SCB_DFSR_BKPT_Pos 1U 626 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) 628 #define SCB_DFSR_HALTED_Pos 0U 629 #define SCB_DFSR_HALTED_Msk (1UL ) 646 uint32_t RESERVED0[1U];
648 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200U)) 649 __IOM uint32_t ACTLR;
651 uint32_t RESERVED1[1U];
656 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U 657 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL ) 661 #define SCnSCB_ACTLR_DISFOLD_Pos 2U 662 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) 664 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U 665 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) 667 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U 668 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL ) 692 #define SysTick_CTRL_COUNTFLAG_Pos 16U 693 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) 695 #define SysTick_CTRL_CLKSOURCE_Pos 2U 696 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) 698 #define SysTick_CTRL_TICKINT_Pos 1U 699 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) 701 #define SysTick_CTRL_ENABLE_Pos 0U 702 #define SysTick_CTRL_ENABLE_Msk (1UL ) 705 #define SysTick_LOAD_RELOAD_Pos 0U 706 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL ) 709 #define SysTick_VAL_CURRENT_Pos 0U 710 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL ) 713 #define SysTick_CALIB_NOREF_Pos 31U 714 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) 716 #define SysTick_CALIB_SKEW_Pos 30U 717 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) 719 #define SysTick_CALIB_TENMS_Pos 0U 720 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL ) 743 uint32_t RESERVED0[864U];
745 uint32_t RESERVED1[15U];
747 uint32_t RESERVED2[15U];
749 uint32_t RESERVED3[29U];
753 uint32_t RESERVED4[43U];
756 uint32_t RESERVED5[6U];
772 #define ITM_TPR_PRIVMASK_Pos 0U 773 #define ITM_TPR_PRIVMASK_Msk (0xFUL ) 776 #define ITM_TCR_BUSY_Pos 23U 777 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) 779 #define ITM_TCR_TraceBusID_Pos 16U 780 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) 782 #define ITM_TCR_GTSFREQ_Pos 10U 783 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) 785 #define ITM_TCR_TSPrescale_Pos 8U 786 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) 788 #define ITM_TCR_SWOENA_Pos 4U 789 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) 791 #define ITM_TCR_DWTENA_Pos 3U 792 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) 794 #define ITM_TCR_SYNCENA_Pos 2U 795 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) 797 #define ITM_TCR_TSENA_Pos 1U 798 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) 800 #define ITM_TCR_ITMENA_Pos 0U 801 #define ITM_TCR_ITMENA_Msk (1UL ) 804 #define ITM_IWR_ATVALIDM_Pos 0U 805 #define ITM_IWR_ATVALIDM_Msk (1UL ) 808 #define ITM_IRR_ATREADYM_Pos 0U 809 #define ITM_IRR_ATREADYM_Msk (1UL ) 812 #define ITM_IMCR_INTEGRATION_Pos 0U 813 #define ITM_IMCR_INTEGRATION_Msk (1UL ) 816 #define ITM_LSR_ByteAcc_Pos 2U 817 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) 819 #define ITM_LSR_Access_Pos 1U 820 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) 822 #define ITM_LSR_Present_Pos 0U 823 #define ITM_LSR_Present_Msk (1UL ) 841 __IOM uint32_t CYCCNT;
842 __IOM uint32_t CPICNT;
843 __IOM uint32_t EXCCNT;
844 __IOM uint32_t SLEEPCNT;
845 __IOM uint32_t LSUCNT;
846 __IOM uint32_t FOLDCNT;
848 __IOM uint32_t COMP0;
849 __IOM uint32_t MASK0;
850 __IOM uint32_t FUNCTION0;
851 uint32_t RESERVED0[1U];
852 __IOM uint32_t COMP1;
853 __IOM uint32_t MASK1;
854 __IOM uint32_t FUNCTION1;
855 uint32_t RESERVED1[1U];
856 __IOM uint32_t COMP2;
857 __IOM uint32_t MASK2;
858 __IOM uint32_t FUNCTION2;
859 uint32_t RESERVED2[1U];
860 __IOM uint32_t COMP3;
861 __IOM uint32_t MASK3;
862 __IOM uint32_t FUNCTION3;
866 #define DWT_CTRL_NUMCOMP_Pos 28U 867 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) 869 #define DWT_CTRL_NOTRCPKT_Pos 27U 870 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) 872 #define DWT_CTRL_NOEXTTRIG_Pos 26U 873 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) 875 #define DWT_CTRL_NOCYCCNT_Pos 25U 876 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) 878 #define DWT_CTRL_NOPRFCNT_Pos 24U 879 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) 881 #define DWT_CTRL_CYCEVTENA_Pos 22U 882 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) 884 #define DWT_CTRL_FOLDEVTENA_Pos 21U 885 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) 887 #define DWT_CTRL_LSUEVTENA_Pos 20U 888 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) 890 #define DWT_CTRL_SLEEPEVTENA_Pos 19U 891 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) 893 #define DWT_CTRL_EXCEVTENA_Pos 18U 894 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) 896 #define DWT_CTRL_CPIEVTENA_Pos 17U 897 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) 899 #define DWT_CTRL_EXCTRCENA_Pos 16U 900 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) 902 #define DWT_CTRL_PCSAMPLENA_Pos 12U 903 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) 905 #define DWT_CTRL_SYNCTAP_Pos 10U 906 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) 908 #define DWT_CTRL_CYCTAP_Pos 9U 909 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) 911 #define DWT_CTRL_POSTINIT_Pos 5U 912 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) 914 #define DWT_CTRL_POSTPRESET_Pos 1U 915 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) 917 #define DWT_CTRL_CYCCNTENA_Pos 0U 918 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL ) 921 #define DWT_CPICNT_CPICNT_Pos 0U 922 #define DWT_CPICNT_CPICNT_Msk (0xFFUL ) 925 #define DWT_EXCCNT_EXCCNT_Pos 0U 926 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL ) 929 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U 930 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL ) 933 #define DWT_LSUCNT_LSUCNT_Pos 0U 934 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL ) 937 #define DWT_FOLDCNT_FOLDCNT_Pos 0U 938 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL ) 941 #define DWT_MASK_MASK_Pos 0U 942 #define DWT_MASK_MASK_Msk (0x1FUL ) 945 #define DWT_FUNCTION_MATCHED_Pos 24U 946 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) 948 #define DWT_FUNCTION_DATAVADDR1_Pos 16U 949 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) 951 #define DWT_FUNCTION_DATAVADDR0_Pos 12U 952 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) 954 #define DWT_FUNCTION_DATAVSIZE_Pos 10U 955 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) 957 #define DWT_FUNCTION_LNK1ENA_Pos 9U 958 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) 960 #define DWT_FUNCTION_DATAVMATCH_Pos 8U 961 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) 963 #define DWT_FUNCTION_CYCMATCH_Pos 7U 964 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) 966 #define DWT_FUNCTION_EMITRANGE_Pos 5U 967 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) 969 #define DWT_FUNCTION_FUNCTION_Pos 0U 970 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL ) 987 __IOM uint32_t SSPSR;
988 __IOM uint32_t CSPSR;
989 uint32_t RESERVED0[2U];
991 uint32_t RESERVED1[55U];
993 uint32_t RESERVED2[131U];
997 uint32_t RESERVED3[759U];
998 __IM uint32_t TRIGGER;
1000 __IM uint32_t ITATBCTR2;
1001 uint32_t RESERVED4[1U];
1002 __IM uint32_t ITATBCTR0;
1003 __IM uint32_t FIFO1;
1004 __IOM uint32_t ITCTRL;
1005 uint32_t RESERVED5[39U];
1006 __IOM uint32_t CLAIMSET;
1007 __IOM uint32_t CLAIMCLR;
1008 uint32_t RESERVED7[8U];
1009 __IM uint32_t DEVID;
1010 __IM uint32_t DEVTYPE;
1014 #define TPI_ACPR_PRESCALER_Pos 0U 1015 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL ) 1018 #define TPI_SPPR_TXMODE_Pos 0U 1019 #define TPI_SPPR_TXMODE_Msk (0x3UL ) 1022 #define TPI_FFSR_FtNonStop_Pos 3U 1023 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) 1025 #define TPI_FFSR_TCPresent_Pos 2U 1026 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) 1028 #define TPI_FFSR_FtStopped_Pos 1U 1029 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) 1031 #define TPI_FFSR_FlInProg_Pos 0U 1032 #define TPI_FFSR_FlInProg_Msk (0x1UL ) 1035 #define TPI_FFCR_TrigIn_Pos 8U 1036 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) 1038 #define TPI_FFCR_EnFCont_Pos 1U 1039 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) 1042 #define TPI_TRIGGER_TRIGGER_Pos 0U 1043 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL ) 1046 #define TPI_FIFO0_ITM_ATVALID_Pos 29U 1047 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) 1049 #define TPI_FIFO0_ITM_bytecount_Pos 27U 1050 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) 1052 #define TPI_FIFO0_ETM_ATVALID_Pos 26U 1053 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) 1055 #define TPI_FIFO0_ETM_bytecount_Pos 24U 1056 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) 1058 #define TPI_FIFO0_ETM2_Pos 16U 1059 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) 1061 #define TPI_FIFO0_ETM1_Pos 8U 1062 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) 1064 #define TPI_FIFO0_ETM0_Pos 0U 1065 #define TPI_FIFO0_ETM0_Msk (0xFFUL ) 1068 #define TPI_ITATBCTR2_ATREADY_Pos 0U 1069 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL ) 1072 #define TPI_FIFO1_ITM_ATVALID_Pos 29U 1073 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) 1075 #define TPI_FIFO1_ITM_bytecount_Pos 27U 1076 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) 1078 #define TPI_FIFO1_ETM_ATVALID_Pos 26U 1079 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) 1081 #define TPI_FIFO1_ETM_bytecount_Pos 24U 1082 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) 1084 #define TPI_FIFO1_ITM2_Pos 16U 1085 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) 1087 #define TPI_FIFO1_ITM1_Pos 8U 1088 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) 1090 #define TPI_FIFO1_ITM0_Pos 0U 1091 #define TPI_FIFO1_ITM0_Msk (0xFFUL ) 1094 #define TPI_ITATBCTR0_ATREADY_Pos 0U 1095 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL ) 1098 #define TPI_ITCTRL_Mode_Pos 0U 1099 #define TPI_ITCTRL_Mode_Msk (0x1UL ) 1102 #define TPI_DEVID_NRZVALID_Pos 11U 1103 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) 1105 #define TPI_DEVID_MANCVALID_Pos 10U 1106 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) 1108 #define TPI_DEVID_PTINVALID_Pos 9U 1109 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) 1111 #define TPI_DEVID_MinBufSz_Pos 6U 1112 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) 1114 #define TPI_DEVID_AsynClkIn_Pos 5U 1115 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) 1117 #define TPI_DEVID_NrTraceInput_Pos 0U 1118 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL ) 1121 #define TPI_DEVTYPE_MajorType_Pos 4U 1122 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) 1124 #define TPI_DEVTYPE_SubType_Pos 0U 1125 #define TPI_DEVTYPE_SubType_Msk (0xFUL ) 1130 #if (__MPU_PRESENT == 1U) 1144 __IOM uint32_t CTRL;
1146 __IOM uint32_t RBAR;
1147 __IOM uint32_t RASR;
1148 __IOM uint32_t RBAR_A1;
1149 __IOM uint32_t RASR_A1;
1150 __IOM uint32_t RBAR_A2;
1151 __IOM uint32_t RASR_A2;
1152 __IOM uint32_t RBAR_A3;
1153 __IOM uint32_t RASR_A3;
1157 #define MPU_TYPE_IREGION_Pos 16U 1158 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) 1160 #define MPU_TYPE_DREGION_Pos 8U 1161 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) 1163 #define MPU_TYPE_SEPARATE_Pos 0U 1164 #define MPU_TYPE_SEPARATE_Msk (1UL ) 1167 #define MPU_CTRL_PRIVDEFENA_Pos 2U 1168 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) 1170 #define MPU_CTRL_HFNMIENA_Pos 1U 1171 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) 1173 #define MPU_CTRL_ENABLE_Pos 0U 1174 #define MPU_CTRL_ENABLE_Msk (1UL ) 1177 #define MPU_RNR_REGION_Pos 0U 1178 #define MPU_RNR_REGION_Msk (0xFFUL ) 1181 #define MPU_RBAR_ADDR_Pos 5U 1182 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) 1184 #define MPU_RBAR_VALID_Pos 4U 1185 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) 1187 #define MPU_RBAR_REGION_Pos 0U 1188 #define MPU_RBAR_REGION_Msk (0xFUL ) 1191 #define MPU_RASR_ATTRS_Pos 16U 1192 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) 1194 #define MPU_RASR_XN_Pos 28U 1195 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) 1197 #define MPU_RASR_AP_Pos 24U 1198 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) 1200 #define MPU_RASR_TEX_Pos 19U 1201 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) 1203 #define MPU_RASR_S_Pos 18U 1204 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) 1206 #define MPU_RASR_C_Pos 17U 1207 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) 1209 #define MPU_RASR_B_Pos 16U 1210 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) 1212 #define MPU_RASR_SRD_Pos 8U 1213 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) 1215 #define MPU_RASR_SIZE_Pos 1U 1216 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) 1218 #define MPU_RASR_ENABLE_Pos 0U 1219 #define MPU_RASR_ENABLE_Msk (1UL ) 1237 __IOM uint32_t DHCSR;
1238 __OM uint32_t DCRSR;
1239 __IOM uint32_t DCRDR;
1240 __IOM uint32_t DEMCR;
1244 #define CoreDebug_DHCSR_DBGKEY_Pos 16U 1245 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) 1247 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U 1248 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) 1250 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U 1251 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) 1253 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U 1254 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) 1256 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U 1257 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) 1259 #define CoreDebug_DHCSR_S_HALT_Pos 17U 1260 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) 1262 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U 1263 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) 1265 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U 1266 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) 1268 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U 1269 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) 1271 #define CoreDebug_DHCSR_C_STEP_Pos 2U 1272 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) 1274 #define CoreDebug_DHCSR_C_HALT_Pos 1U 1275 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) 1277 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U 1278 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL ) 1281 #define CoreDebug_DCRSR_REGWnR_Pos 16U 1282 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) 1284 #define CoreDebug_DCRSR_REGSEL_Pos 0U 1285 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL ) 1288 #define CoreDebug_DEMCR_TRCENA_Pos 24U 1289 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) 1291 #define CoreDebug_DEMCR_MON_REQ_Pos 19U 1292 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) 1294 #define CoreDebug_DEMCR_MON_STEP_Pos 18U 1295 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) 1297 #define CoreDebug_DEMCR_MON_PEND_Pos 17U 1298 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) 1300 #define CoreDebug_DEMCR_MON_EN_Pos 16U 1301 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) 1303 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U 1304 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) 1306 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U 1307 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) 1309 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U 1310 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) 1312 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U 1313 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) 1315 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U 1316 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) 1318 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U 1319 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) 1321 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U 1322 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) 1324 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U 1325 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL ) 1343 #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) 1351 #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) 1364 #define SCS_BASE (0xE000E000UL) 1365 #define ITM_BASE (0xE0000000UL) 1366 #define DWT_BASE (0xE0001000UL) 1367 #define TPI_BASE (0xE0040000UL) 1368 #define CoreDebug_BASE (0xE000EDF0UL) 1369 #define SysTick_BASE (SCS_BASE + 0x0010UL) 1370 #define NVIC_BASE (SCS_BASE + 0x0100UL) 1371 #define SCB_BASE (SCS_BASE + 0x0D00UL) 1373 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) 1374 #define SCB ((SCB_Type *) SCB_BASE ) 1375 #define SysTick ((SysTick_Type *) SysTick_BASE ) 1376 #define NVIC ((NVIC_Type *) NVIC_BASE ) 1377 #define ITM ((ITM_Type *) ITM_BASE ) 1378 #define DWT ((DWT_Type *) DWT_BASE ) 1379 #define TPI ((TPI_Type *) TPI_BASE ) 1380 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) 1382 #if (__MPU_PRESENT == 1U) 1383 #define MPU_BASE (SCS_BASE + 0x0D90UL) 1384 #define MPU ((MPU_Type *) MPU_BASE ) 1425 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);
1427 reg_value =
SCB->AIRCR;
1429 reg_value = (reg_value |
1431 (PriorityGroupTmp << 8U) );
1432 SCB->AIRCR = reg_value;
1456 return((uint32_t)(((
NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1467 NVIC->ISER[(((uint32_t)(int32_t)
IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1478 NVIC->ICER[(((uint32_t)(int32_t)
IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1491 return((uint32_t)(((
NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1502 NVIC->ISPR[(((uint32_t)(int32_t)
IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1513 NVIC->ICPR[(((uint32_t)(int32_t)
IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1526 return((uint32_t)(((
NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1539 if ((int32_t)(IRQn) < 0)
1541 SCB->SHP[(((uint32_t)(int32_t)
IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U -
__NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1562 if ((int32_t)(IRQn) < 0)
1564 return(((uint32_t)
SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U -
__NVIC_PRIO_BITS)));
1584 __STATIC_INLINE uint32_t
NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1586 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);
1587 uint32_t PreemptPriorityBits;
1588 uint32_t SubPriorityBits;
1591 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(
__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(
__NVIC_PRIO_BITS));
1594 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1595 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1611 __STATIC_INLINE
void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t*
const pPreemptPriority, uint32_t*
const pSubPriority)
1613 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);
1614 uint32_t PreemptPriorityBits;
1615 uint32_t SubPriorityBits;
1618 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(
__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(
__NVIC_PRIO_BITS));
1620 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1621 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1656 #if (__Vendor_SysTickConfig == 0U) 1676 SysTick->LOAD = (uint32_t)(ticks - 1UL);
1700 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5U 1714 ((
ITM->TER & 1UL ) != 0UL) )
1716 while (
ITM->PORT[0U].u32 == 0UL)
1720 ITM->PORT[0U].u8 = (uint8_t)ch;
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
CMSIS Cortex-M Core Function Access Header File.
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
#define SCB_AIRCR_VECTKEY_Pos
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
#define SysTick_CTRL_CLKSOURCE_Msk
Structure type to access the System Control Block (SCB).
Structure type to access the Data Watchpoint and Trace Register (DWT).
CMSIS Cortex-M Core Instruction Access Header File.
__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch)
ITM Send Character.
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
#define ITM_RXBUFFER_EMPTY
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
volatile int32_t ITM_RxBuffer
#define SysTick_CTRL_TICKINT_Msk
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Disable External Interrupt.
Structure type to access the System Timer (SysTick).
Structure type to access the Core Debug Register (CoreDebug).
__STATIC_INLINE void NVIC_SystemReset(void)
System Reset.
Union type to access the Application Program Status Register (APSR).
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Enable External Interrupt.
#define SCB_AIRCR_VECTKEY_Msk
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
__STATIC_INLINE uint32_t NVIC_IsIRQEnabled(IRQn_Type IRQn)
Get External Interrupt Enable State.
__STATIC_INLINE void __NOP(void)
No Operation.
#define SCB_AIRCR_PRIGROUP_Msk
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
System Tick Configuration.
Union type to access the Control Registers (CONTROL).
Structure type to access the Trace Port Interface Register (TPI).
#define SysTick_LOAD_RELOAD_Msk
Structure type to access the System Control and ID Register not in the SCB.
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
__STATIC_INLINE void __DSB(void)
Data Synchronization Barrier.
Union type to access the Interrupt Program Status Register (IPSR).
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Union type to access the Special-Purpose Program Status Registers (xPSR).
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
#define SysTick_CTRL_ENABLE_Msk
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
#define __NVIC_PRIO_BITS
Number of Bits used for Priority Levels.
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
#define ITM_TCR_ITMENA_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
#define SCB_AIRCR_PRIGROUP_Pos