ITM_Type Struct Reference

Structure type to access the Instrumentation Trace Macrocell Register (ITM). More...

#include <arch/cpu/arm/cortex-m/CMSIS/core_cm3.h>

Data Fields
union {
__OM uint8_t   u8
__OM uint16_t   u16
__OM uint32_t   u32
}	PORT [32U]
__IOM uint32_t	TER
__IOM uint32_t	TPR
__IOM uint32_t	TCR
__OM uint32_t	IWR
__IM uint32_t	IRR
__IOM uint32_t	IMCR
__OM uint32_t	LAR
__IM uint32_t	LSR
__IM uint32_t	PID4
__IM uint32_t	PID5
__IM uint32_t	PID6
__IM uint32_t	PID7
__IM uint32_t	PID0
__IM uint32_t	PID1
__IM uint32_t	PID2
__IM uint32_t	PID3
__IM uint32_t	CID0
__IM uint32_t	CID1
__IM uint32_t	CID2
__IM uint32_t	CID3
union {
__OM uint8_t   u8
__OM uint16_t   u16
__OM uint32_t   u32
}	PORT [32U]
union {
__OM uint8_t   u8
__OM uint16_t   u16
__OM uint32_t   u32
}	PORT [32U]
union {
__OM uint8_t   u8
__OM uint16_t   u16
__OM uint32_t   u32
}	PORT [32U]

Detailed Description

Structure type to access the Instrumentation Trace Macrocell Register (ITM).

Definition at line 735 of file core_cm3.h.

Field Documentation

CID0

__IM uint32_t ITM_Type::CID0

Offset: 0xFF0 (R/ ) ITM Component Identification Register #0

Definition at line 765 of file core_cm3.h.

CID1

__IM uint32_t ITM_Type::CID1

Offset: 0xFF4 (R/ ) ITM Component Identification Register #1

Definition at line 766 of file core_cm3.h.

CID2

__IM uint32_t ITM_Type::CID2

Offset: 0xFF8 (R/ ) ITM Component Identification Register #2

Definition at line 767 of file core_cm3.h.

CID3

__IM uint32_t ITM_Type::CID3

Offset: 0xFFC (R/ ) ITM Component Identification Register #3

Definition at line 768 of file core_cm3.h.

IMCR

__IOM uint32_t ITM_Type::IMCR

Offset: 0xF00 (R/W) ITM Integration Mode Control Register

Definition at line 752 of file core_cm3.h.

IRR

__IM uint32_t ITM_Type::IRR

Offset: 0xEFC (R/ ) ITM Integration Read Register

Definition at line 751 of file core_cm3.h.

IWR

__OM uint32_t ITM_Type::IWR

Offset: 0xEF8 ( /W) ITM Integration Write Register

Definition at line 750 of file core_cm3.h.

LAR

__OM uint32_t ITM_Type::LAR

Offset: 0xFB0 ( /W) ITM Lock Access Register

Definition at line 754 of file core_cm3.h.

LSR

__IM uint32_t ITM_Type::LSR

Offset: 0xFB4 (R/ ) ITM Lock Status Register

Definition at line 755 of file core_cm3.h.

PID0

__IM uint32_t ITM_Type::PID0

Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0

Definition at line 761 of file core_cm3.h.

PID1

__IM uint32_t ITM_Type::PID1

Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1

Definition at line 762 of file core_cm3.h.

PID2

__IM uint32_t ITM_Type::PID2

Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2

Definition at line 763 of file core_cm3.h.

PID3

__IM uint32_t ITM_Type::PID3

Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3

Definition at line 764 of file core_cm3.h.

PID4

__IM uint32_t ITM_Type::PID4

Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4

Definition at line 757 of file core_cm3.h.

PID5

__IM uint32_t ITM_Type::PID5

Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5

Definition at line 758 of file core_cm3.h.

PID6

__IM uint32_t ITM_Type::PID6

Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6

Definition at line 759 of file core_cm3.h.

PID7

__IM uint32_t ITM_Type::PID7

Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7

Definition at line 760 of file core_cm3.h.

PORT [1/4]

__OM { ... } ITM_Type::PORT[32U]

Offset: 0x000 ( /W) ITM Stimulus Port Registers

PORT [2/4]

__OM { ... } ITM_Type::PORT[32U]

Offset: 0x000 ( /W) ITM Stimulus Port Registers

PORT [3/4]

__OM { ... } ITM_Type::PORT[32U]

Offset: 0x000 ( /W) ITM Stimulus Port Registers

PORT [4/4]

__OM { ... } ITM_Type::PORT[32U]

Offset: 0x000 ( /W) ITM Stimulus Port Registers

TCR

__IOM uint32_t ITM_Type::TCR

Offset: 0xE80 (R/W) ITM Trace Control Register

Definition at line 748 of file core_cm3.h.

TER

__IOM uint32_t ITM_Type::TER

Offset: 0xE00 (R/W) ITM Trace Enable Register

Definition at line 744 of file core_cm3.h.

TPR

__IOM uint32_t ITM_Type::TPR

Offset: 0xE40 (R/W) ITM Trace Privilege Register

Definition at line 746 of file core_cm3.h.

u16

__OM uint16_t ITM_Type::u16

Offset: 0x000 ( /W) ITM Stimulus Port 16-bit

Definition at line 740 of file core_cm3.h.

u32

__OM uint32_t ITM_Type::u32

Offset: 0x000 ( /W) ITM Stimulus Port 32-bit

Definition at line 741 of file core_cm3.h.

u8

__OM uint8_t ITM_Type::u8

Offset: 0x000 ( /W) ITM Stimulus Port 8-bit

Definition at line 739 of file core_cm3.h.