Type definitions for the System Control Block Registers. More...

Data Structures
struct	SCB_Type
	Structure type to access the System Control Block (SCB). More...

Macros
#define	SCB_CPUID_IMPLEMENTER_Pos 24U

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_VARIANT_Pos 20U

#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_ARCHITECTURE_Pos 16U

#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define	SCB_CPUID_PARTNO_Pos 4U

#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_REVISION_Pos 0U

#define	SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/)

#define	SCB_ICSR_NMIPENDSET_Pos 31U

#define	SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)

#define	SCB_ICSR_PENDSVSET_Pos 28U

#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27U

#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26U

#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25U

#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23U

#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22U

#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12U

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_VECTACTIVE_Pos 0U

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/)

#define	SCB_AIRCR_VECTKEY_Pos 16U

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16U

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15U

#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2U

#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1U

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_SCR_SEVONPEND_Pos 4U

#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2U

#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1U

#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_CCR_STKALIGN_Pos 9U

#define	SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3U

#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15U

#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SCB_CPUID_IMPLEMENTER_Pos 24U

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_VARIANT_Pos 20U

#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_ARCHITECTURE_Pos 16U

#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define	SCB_CPUID_PARTNO_Pos 4U

#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_REVISION_Pos 0U

#define	SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/)

#define	SCB_ICSR_NMIPENDSET_Pos 31U

#define	SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)

#define	SCB_ICSR_PENDSVSET_Pos 28U

#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27U

#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26U

#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25U

#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23U

#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22U

#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12U

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_VECTACTIVE_Pos 0U

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/)

#define	SCB_AIRCR_VECTKEY_Pos 16U

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16U

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15U

#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2U

#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1U

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_SCR_SEVONPEND_Pos 4U

#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2U

#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1U

#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_CCR_STKALIGN_Pos 9U

#define	SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3U

#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15U

#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SCB_CPUID_IMPLEMENTER_Pos 24U

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_VARIANT_Pos 20U

#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_ARCHITECTURE_Pos 16U

#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define	SCB_CPUID_PARTNO_Pos 4U

#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_REVISION_Pos 0U

#define	SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/)

#define	SCB_ICSR_NMIPENDSET_Pos 31U

#define	SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)

#define	SCB_ICSR_PENDSVSET_Pos 28U

#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27U

#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26U

#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25U

#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23U

#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22U

#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12U

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_RETTOBASE_Pos 11U

#define	SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

#define	SCB_ICSR_VECTACTIVE_Pos 0U

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/)

#define	SCB_VTOR_TBLBASE_Pos 29U

#define	SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos)

#define	SCB_VTOR_TBLOFF_Pos 7U

#define	SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)

#define	SCB_AIRCR_VECTKEY_Pos 16U

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16U

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15U

#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_PRIGROUP_Pos 8U

#define	SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2U

#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1U

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_AIRCR_VECTRESET_Pos 0U

#define	SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/)

#define	SCB_SCR_SEVONPEND_Pos 4U

#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2U

#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1U

#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_CCR_STKALIGN_Pos 9U

#define	SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

#define	SCB_CCR_BFHFNMIGN_Pos 8U

#define	SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

#define	SCB_CCR_DIV_0_TRP_Pos 4U

#define	SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3U

#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_CCR_USERSETMPEND_Pos 1U

#define	SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

#define	SCB_CCR_NONBASETHRDENA_Pos 0U

#define	SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/)

#define	SCB_SHCSR_USGFAULTENA_Pos 18U

#define	SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

#define	SCB_SHCSR_BUSFAULTENA_Pos 17U

#define	SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

#define	SCB_SHCSR_MEMFAULTENA_Pos 16U

#define	SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15U

#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SCB_SHCSR_BUSFAULTPENDED_Pos 14U

#define	SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

#define	SCB_SHCSR_MEMFAULTPENDED_Pos 13U

#define	SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

#define	SCB_SHCSR_USGFAULTPENDED_Pos 12U

#define	SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

#define	SCB_SHCSR_SYSTICKACT_Pos 11U

#define	SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

#define	SCB_SHCSR_PENDSVACT_Pos 10U

#define	SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

#define	SCB_SHCSR_MONITORACT_Pos 8U

#define	SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

#define	SCB_SHCSR_SVCALLACT_Pos 7U

#define	SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

#define	SCB_SHCSR_USGFAULTACT_Pos 3U

#define	SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

#define	SCB_SHCSR_BUSFAULTACT_Pos 1U

#define	SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

#define	SCB_SHCSR_MEMFAULTACT_Pos 0U

#define	SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/)

#define	SCB_CFSR_USGFAULTSR_Pos 16U

#define	SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

#define	SCB_CFSR_BUSFAULTSR_Pos 8U

#define	SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

#define	SCB_CFSR_MEMFAULTSR_Pos 0U

#define	SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/)

#define	SCB_HFSR_DEBUGEVT_Pos 31U

#define	SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

#define	SCB_HFSR_FORCED_Pos 30U

#define	SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

#define	SCB_HFSR_VECTTBL_Pos 1U

#define	SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

#define	SCB_DFSR_EXTERNAL_Pos 4U

#define	SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

#define	SCB_DFSR_VCATCH_Pos 3U

#define	SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

#define	SCB_DFSR_DWTTRAP_Pos 2U

#define	SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

#define	SCB_DFSR_BKPT_Pos 1U

#define	SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

#define	SCB_DFSR_HALTED_Pos 0U

#define	SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/)

#define	SCB_CPUID_IMPLEMENTER_Pos 24U

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_VARIANT_Pos 20U

#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_ARCHITECTURE_Pos 16U

#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define	SCB_CPUID_PARTNO_Pos 4U

#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_REVISION_Pos 0U

#define	SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/)

#define	SCB_ICSR_NMIPENDSET_Pos 31U

#define	SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)

#define	SCB_ICSR_PENDSVSET_Pos 28U

#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27U

#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26U

#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25U

#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23U

#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22U

#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12U

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_RETTOBASE_Pos 11U

#define	SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

#define	SCB_ICSR_VECTACTIVE_Pos 0U

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/)

#define	SCB_VTOR_TBLOFF_Pos 7U

#define	SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

#define	SCB_AIRCR_VECTKEY_Pos 16U

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16U

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15U

#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_PRIGROUP_Pos 8U

#define	SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2U

#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1U

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_AIRCR_VECTRESET_Pos 0U

#define	SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/)

#define	SCB_SCR_SEVONPEND_Pos 4U

#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2U

#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1U

#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_CCR_STKALIGN_Pos 9U

#define	SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

#define	SCB_CCR_BFHFNMIGN_Pos 8U

#define	SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

#define	SCB_CCR_DIV_0_TRP_Pos 4U

#define	SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3U

#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_CCR_USERSETMPEND_Pos 1U

#define	SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

#define	SCB_CCR_NONBASETHRDENA_Pos 0U

#define	SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/)

#define	SCB_SHCSR_USGFAULTENA_Pos 18U

#define	SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

#define	SCB_SHCSR_BUSFAULTENA_Pos 17U

#define	SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

#define	SCB_SHCSR_MEMFAULTENA_Pos 16U

#define	SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15U

#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SCB_SHCSR_BUSFAULTPENDED_Pos 14U

#define	SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

#define	SCB_SHCSR_MEMFAULTPENDED_Pos 13U

#define	SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

#define	SCB_SHCSR_USGFAULTPENDED_Pos 12U

#define	SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

#define	SCB_SHCSR_SYSTICKACT_Pos 11U

#define	SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

#define	SCB_SHCSR_PENDSVACT_Pos 10U

#define	SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

#define	SCB_SHCSR_MONITORACT_Pos 8U

#define	SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

#define	SCB_SHCSR_SVCALLACT_Pos 7U

#define	SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

#define	SCB_SHCSR_USGFAULTACT_Pos 3U

#define	SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

#define	SCB_SHCSR_BUSFAULTACT_Pos 1U

#define	SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

#define	SCB_SHCSR_MEMFAULTACT_Pos 0U

#define	SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/)

#define	SCB_CFSR_USGFAULTSR_Pos 16U

#define	SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

#define	SCB_CFSR_BUSFAULTSR_Pos 8U

#define	SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

#define	SCB_CFSR_MEMFAULTSR_Pos 0U

#define	SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/)

#define	SCB_HFSR_DEBUGEVT_Pos 31U

#define	SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

#define	SCB_HFSR_FORCED_Pos 30U

#define	SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

#define	SCB_HFSR_VECTTBL_Pos 1U

#define	SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

#define	SCB_DFSR_EXTERNAL_Pos 4U

#define	SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

#define	SCB_DFSR_VCATCH_Pos 3U

#define	SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

#define	SCB_DFSR_DWTTRAP_Pos 2U

#define	SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

#define	SCB_DFSR_BKPT_Pos 1U

#define	SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

#define	SCB_DFSR_HALTED_Pos 0U

#define	SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/)

#define	SCB_CPUID_IMPLEMENTER_Pos 24U

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_VARIANT_Pos 20U

#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_ARCHITECTURE_Pos 16U

#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define	SCB_CPUID_PARTNO_Pos 4U

#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_REVISION_Pos 0U

#define	SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/)

#define	SCB_ICSR_NMIPENDSET_Pos 31U

#define	SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)

#define	SCB_ICSR_PENDSVSET_Pos 28U

#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27U

#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26U

#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25U

#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23U

#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22U

#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12U

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_RETTOBASE_Pos 11U

#define	SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

#define	SCB_ICSR_VECTACTIVE_Pos 0U

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/)

#define	SCB_VTOR_TBLOFF_Pos 7U

#define	SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

#define	SCB_AIRCR_VECTKEY_Pos 16U

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16U

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15U

#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_PRIGROUP_Pos 8U

#define	SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2U

#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1U

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_AIRCR_VECTRESET_Pos 0U

#define	SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/)

#define	SCB_SCR_SEVONPEND_Pos 4U

#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2U

#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1U

#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_CCR_BP_Pos 18U

#define	SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)

#define	SCB_CCR_IC_Pos 17U

#define	SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)

#define	SCB_CCR_DC_Pos 16U

#define	SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)

#define	SCB_CCR_STKALIGN_Pos 9U

#define	SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

#define	SCB_CCR_BFHFNMIGN_Pos 8U

#define	SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

#define	SCB_CCR_DIV_0_TRP_Pos 4U

#define	SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3U

#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_CCR_USERSETMPEND_Pos 1U

#define	SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

#define	SCB_CCR_NONBASETHRDENA_Pos 0U

#define	SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/)

#define	SCB_SHCSR_USGFAULTENA_Pos 18U

#define	SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

#define	SCB_SHCSR_BUSFAULTENA_Pos 17U

#define	SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

#define	SCB_SHCSR_MEMFAULTENA_Pos 16U

#define	SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15U

#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SCB_SHCSR_BUSFAULTPENDED_Pos 14U

#define	SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

#define	SCB_SHCSR_MEMFAULTPENDED_Pos 13U

#define	SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

#define	SCB_SHCSR_USGFAULTPENDED_Pos 12U

#define	SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

#define	SCB_SHCSR_SYSTICKACT_Pos 11U

#define	SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

#define	SCB_SHCSR_PENDSVACT_Pos 10U

#define	SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

#define	SCB_SHCSR_MONITORACT_Pos 8U

#define	SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

#define	SCB_SHCSR_SVCALLACT_Pos 7U

#define	SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

#define	SCB_SHCSR_USGFAULTACT_Pos 3U

#define	SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

#define	SCB_SHCSR_BUSFAULTACT_Pos 1U

#define	SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

#define	SCB_SHCSR_MEMFAULTACT_Pos 0U

#define	SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/)

#define	SCB_CFSR_USGFAULTSR_Pos 16U

#define	SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

#define	SCB_CFSR_BUSFAULTSR_Pos 8U

#define	SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

#define	SCB_CFSR_MEMFAULTSR_Pos 0U

#define	SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/)

#define	SCB_HFSR_DEBUGEVT_Pos 31U

#define	SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

#define	SCB_HFSR_FORCED_Pos 30U

#define	SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

#define	SCB_HFSR_VECTTBL_Pos 1U

#define	SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

#define	SCB_DFSR_EXTERNAL_Pos 4U

#define	SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

#define	SCB_DFSR_VCATCH_Pos 3U

#define	SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

#define	SCB_DFSR_DWTTRAP_Pos 2U

#define	SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

#define	SCB_DFSR_BKPT_Pos 1U

#define	SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

#define	SCB_DFSR_HALTED_Pos 0U

#define	SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/)

#define	SCB_CLIDR_LOUU_Pos 27U

#define	SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)

#define	SCB_CLIDR_LOC_Pos 24U

#define	SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)

#define	SCB_CTR_FORMAT_Pos 29U

#define	SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)

#define	SCB_CTR_CWG_Pos 24U

#define	SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)

#define	SCB_CTR_ERG_Pos 20U

#define	SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)

#define	SCB_CTR_DMINLINE_Pos 16U

#define	SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)

#define	SCB_CTR_IMINLINE_Pos 0U

#define	SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/)

#define	SCB_CCSIDR_WT_Pos 31U

#define	SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)

#define	SCB_CCSIDR_WB_Pos 30U

#define	SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)

#define	SCB_CCSIDR_RA_Pos 29U

#define	SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)

#define	SCB_CCSIDR_WA_Pos 28U

#define	SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)

#define	SCB_CCSIDR_NUMSETS_Pos 13U

#define	SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

#define	SCB_CCSIDR_ASSOCIATIVITY_Pos 3U

#define	SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

#define	SCB_CCSIDR_LINESIZE_Pos 0U

#define	SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/)

#define	SCB_CSSELR_LEVEL_Pos 1U

#define	SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)

#define	SCB_CSSELR_IND_Pos 0U

#define	SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/)

#define	SCB_STIR_INTID_Pos 0U

#define	SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/)

#define	SCB_DCISW_WAY_Pos 30U

#define	SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)

#define	SCB_DCISW_SET_Pos 5U

#define	SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)

#define	SCB_DCCSW_WAY_Pos 30U

#define	SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)

#define	SCB_DCCSW_SET_Pos 5U

#define	SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)

#define	SCB_DCCISW_WAY_Pos 30U

#define	SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)

#define	SCB_DCCISW_SET_Pos 5U

#define	SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)

#define	SCB_ITCMCR_SZ_Pos 3U

#define	SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos)

#define	SCB_ITCMCR_RETEN_Pos 2U

#define	SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos)

#define	SCB_ITCMCR_RMW_Pos 1U

#define	SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos)

#define	SCB_ITCMCR_EN_Pos 0U

#define	SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/)

#define	SCB_DTCMCR_SZ_Pos 3U

#define	SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos)

#define	SCB_DTCMCR_RETEN_Pos 2U

#define	SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos)

#define	SCB_DTCMCR_RMW_Pos 1U

#define	SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos)

#define	SCB_DTCMCR_EN_Pos 0U

#define	SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/)

#define	SCB_AHBPCR_SZ_Pos 1U

#define	SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos)

#define	SCB_AHBPCR_EN_Pos 0U

#define	SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/)

#define	SCB_CACR_FORCEWT_Pos 2U

#define	SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos)

#define	SCB_CACR_ECCEN_Pos 1U

#define	SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos)

#define	SCB_CACR_SIWT_Pos 0U

#define	SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/)

#define	SCB_AHBSCR_INITCOUNT_Pos 11U

#define	SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)

#define	SCB_AHBSCR_TPRI_Pos 2U

#define	SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos)

#define	SCB_AHBSCR_CTL_Pos 0U

#define	SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/)

#define	SCB_ABFSR_AXIMTYPE_Pos 8U

#define	SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos)

#define	SCB_ABFSR_EPPB_Pos 4U

#define	SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos)

#define	SCB_ABFSR_AXIM_Pos 3U

#define	SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos)

#define	SCB_ABFSR_AHBP_Pos 2U

#define	SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos)

#define	SCB_ABFSR_DTCM_Pos 1U

#define	SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos)

#define	SCB_ABFSR_ITCM_Pos 0U

#define	SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/)

#define	SCB_CPUID_IMPLEMENTER_Pos 24U

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_VARIANT_Pos 20U

#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_ARCHITECTURE_Pos 16U

#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define	SCB_CPUID_PARTNO_Pos 4U

#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_REVISION_Pos 0U

#define	SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/)

#define	SCB_ICSR_NMIPENDSET_Pos 31U

#define	SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)

#define	SCB_ICSR_PENDSVSET_Pos 28U

#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27U

#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26U

#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25U

#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23U

#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22U

#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12U

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_VECTACTIVE_Pos 0U

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/)

#define	SCB_VTOR_TBLOFF_Pos 7U

#define	SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

#define	SCB_AIRCR_VECTKEY_Pos 16U

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16U

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15U

#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2U

#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1U

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_SCR_SEVONPEND_Pos 4U

#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2U

#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1U

#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_CCR_STKALIGN_Pos 9U

#define	SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3U

#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15U

#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SCB_CPUID_IMPLEMENTER_Pos 24U

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_VARIANT_Pos 20U

#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_ARCHITECTURE_Pos 16U

#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define	SCB_CPUID_PARTNO_Pos 4U

#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_REVISION_Pos 0U

#define	SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/)

#define	SCB_ICSR_NMIPENDSET_Pos 31U

#define	SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)

#define	SCB_ICSR_PENDSVSET_Pos 28U

#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27U

#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26U

#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25U

#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23U

#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22U

#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12U

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_RETTOBASE_Pos 11U

#define	SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

#define	SCB_ICSR_VECTACTIVE_Pos 0U

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/)

#define	SCB_VTOR_TBLBASE_Pos 29U

#define	SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos)

#define	SCB_VTOR_TBLOFF_Pos 7U

#define	SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)

#define	SCB_AIRCR_VECTKEY_Pos 16U

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16U

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15U

#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_PRIGROUP_Pos 8U

#define	SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2U

#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1U

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_AIRCR_VECTRESET_Pos 0U

#define	SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/)

#define	SCB_SCR_SEVONPEND_Pos 4U

#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2U

#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1U

#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_CCR_STKALIGN_Pos 9U

#define	SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

#define	SCB_CCR_BFHFNMIGN_Pos 8U

#define	SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

#define	SCB_CCR_DIV_0_TRP_Pos 4U

#define	SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3U

#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_CCR_USERSETMPEND_Pos 1U

#define	SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

#define	SCB_CCR_NONBASETHRDENA_Pos 0U

#define	SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/)

#define	SCB_SHCSR_USGFAULTENA_Pos 18U

#define	SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

#define	SCB_SHCSR_BUSFAULTENA_Pos 17U

#define	SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

#define	SCB_SHCSR_MEMFAULTENA_Pos 16U

#define	SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15U

#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SCB_SHCSR_BUSFAULTPENDED_Pos 14U

#define	SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

#define	SCB_SHCSR_MEMFAULTPENDED_Pos 13U

#define	SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

#define	SCB_SHCSR_USGFAULTPENDED_Pos 12U

#define	SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

#define	SCB_SHCSR_SYSTICKACT_Pos 11U

#define	SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

#define	SCB_SHCSR_PENDSVACT_Pos 10U

#define	SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

#define	SCB_SHCSR_MONITORACT_Pos 8U

#define	SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

#define	SCB_SHCSR_SVCALLACT_Pos 7U

#define	SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

#define	SCB_SHCSR_USGFAULTACT_Pos 3U

#define	SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

#define	SCB_SHCSR_BUSFAULTACT_Pos 1U

#define	SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

#define	SCB_SHCSR_MEMFAULTACT_Pos 0U

#define	SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/)

#define	SCB_CFSR_USGFAULTSR_Pos 16U

#define	SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

#define	SCB_CFSR_BUSFAULTSR_Pos 8U

#define	SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

#define	SCB_CFSR_MEMFAULTSR_Pos 0U

#define	SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/)

#define	SCB_HFSR_DEBUGEVT_Pos 31U

#define	SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

#define	SCB_HFSR_FORCED_Pos 30U

#define	SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

#define	SCB_HFSR_VECTTBL_Pos 1U

#define	SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

#define	SCB_DFSR_EXTERNAL_Pos 4U

#define	SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

#define	SCB_DFSR_VCATCH_Pos 3U

#define	SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

#define	SCB_DFSR_DWTTRAP_Pos 2U

#define	SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

#define	SCB_DFSR_BKPT_Pos 1U

#define	SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

#define	SCB_DFSR_HALTED_Pos 0U

#define	SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/)

Detailed Description

Type definitions for the System Control Block Registers.

Macro Definition Documentation

◆ SCB_ABFSR_AHBP_Msk

#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos)

SCB ABFSR: AHBP Mask

Definition at line 885 of file core_cm7.h.

◆ SCB_ABFSR_AHBP_Pos

#define SCB_ABFSR_AHBP_Pos 2U

SCB ABFSR: AHBP Position

Definition at line 884 of file core_cm7.h.

◆ SCB_ABFSR_AXIM_Msk

#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos)

SCB ABFSR: AXIM Mask

Definition at line 882 of file core_cm7.h.

◆ SCB_ABFSR_AXIM_Pos

#define SCB_ABFSR_AXIM_Pos 3U

SCB ABFSR: AXIM Position

Definition at line 881 of file core_cm7.h.

◆ SCB_ABFSR_AXIMTYPE_Msk

#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos)

SCB ABFSR: AXIMTYPE Mask

Definition at line 876 of file core_cm7.h.

◆ SCB_ABFSR_AXIMTYPE_Pos

#define SCB_ABFSR_AXIMTYPE_Pos 8U

SCB ABFSR: AXIMTYPE Position

Definition at line 875 of file core_cm7.h.

◆ SCB_ABFSR_DTCM_Msk

#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos)

SCB ABFSR: DTCM Mask

Definition at line 888 of file core_cm7.h.

◆ SCB_ABFSR_DTCM_Pos

#define SCB_ABFSR_DTCM_Pos 1U

SCB ABFSR: DTCM Position

Definition at line 887 of file core_cm7.h.

◆ SCB_ABFSR_EPPB_Msk

#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos)

SCB ABFSR: EPPB Mask

Definition at line 879 of file core_cm7.h.

◆ SCB_ABFSR_EPPB_Pos

#define SCB_ABFSR_EPPB_Pos 4U

SCB ABFSR: EPPB Position

Definition at line 878 of file core_cm7.h.

◆ SCB_ABFSR_ITCM_Msk

#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/)

SCB ABFSR: ITCM Mask

Definition at line 891 of file core_cm7.h.

◆ SCB_ABFSR_ITCM_Pos

#define SCB_ABFSR_ITCM_Pos 0U

SCB ABFSR: ITCM Position

Definition at line 890 of file core_cm7.h.

◆ SCB_AHBPCR_EN_Msk

#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/)

SCB AHBPCR: EN Mask

Definition at line 852 of file core_cm7.h.

◆ SCB_AHBPCR_EN_Pos

#define SCB_AHBPCR_EN_Pos 0U

SCB AHBPCR: EN Position

Definition at line 851 of file core_cm7.h.

◆ SCB_AHBPCR_SZ_Msk

#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos)

SCB AHBPCR: SZ Mask

Definition at line 849 of file core_cm7.h.

◆ SCB_AHBPCR_SZ_Pos

#define SCB_AHBPCR_SZ_Pos 1U

SCB AHBPCR: SZ Position

Definition at line 848 of file core_cm7.h.

◆ SCB_AHBSCR_CTL_Msk

#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/)

SCB AHBSCR: CTL Mask

Definition at line 872 of file core_cm7.h.

◆ SCB_AHBSCR_CTL_Pos

#define SCB_AHBSCR_CTL_Pos 0U

SCB AHBSCR: CTL Position

Definition at line 871 of file core_cm7.h.

◆ SCB_AHBSCR_INITCOUNT_Msk

#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)

SCB AHBSCR: INITCOUNT Mask

Definition at line 866 of file core_cm7.h.

◆ SCB_AHBSCR_INITCOUNT_Pos

#define SCB_AHBSCR_INITCOUNT_Pos 11U

SCB AHBSCR: INITCOUNT Position

Definition at line 865 of file core_cm7.h.

◆ SCB_AHBSCR_TPRI_Msk

#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos)

SCB AHBSCR: TPRI Mask

Definition at line 869 of file core_cm7.h.

◆ SCB_AHBSCR_TPRI_Pos

#define SCB_AHBSCR_TPRI_Pos 2U

SCB AHBSCR: TPRI Position

Definition at line 868 of file core_cm7.h.

◆ SCB_AIRCR_ENDIANESS_Msk [1/7]

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 454 of file core_cm0.h.

◆ SCB_AIRCR_ENDIANESS_Msk [2/7]

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 466 of file core_sc000.h.

◆ SCB_AIRCR_ENDIANESS_Msk [3/7]

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 478 of file core_cm0plus.h.

◆ SCB_AIRCR_ENDIANESS_Msk [4/7]

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 506 of file core_sc300.h.

◆ SCB_AIRCR_ENDIANESS_Msk [5/7]

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 509 of file core_cm3.h.

◆ SCB_AIRCR_ENDIANESS_Msk [6/7]

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 569 of file core_cm4.h.

◆ SCB_AIRCR_ENDIANESS_Msk [7/7]

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 613 of file core_cm7.h.

◆ SCB_AIRCR_ENDIANESS_Pos [1/7]

#define SCB_AIRCR_ENDIANESS_Pos 15U

SCB AIRCR: ENDIANESS Position

Definition at line 453 of file core_cm0.h.

◆ SCB_AIRCR_ENDIANESS_Pos [2/7]

#define SCB_AIRCR_ENDIANESS_Pos 15U

SCB AIRCR: ENDIANESS Position

Definition at line 465 of file core_sc000.h.

◆ SCB_AIRCR_ENDIANESS_Pos [3/7]

#define SCB_AIRCR_ENDIANESS_Pos 15U

SCB AIRCR: ENDIANESS Position

Definition at line 477 of file core_cm0plus.h.

◆ SCB_AIRCR_ENDIANESS_Pos [4/7]

#define SCB_AIRCR_ENDIANESS_Pos 15U

SCB AIRCR: ENDIANESS Position

Definition at line 505 of file core_sc300.h.

◆ SCB_AIRCR_ENDIANESS_Pos [5/7]

#define SCB_AIRCR_ENDIANESS_Pos 15U

SCB AIRCR: ENDIANESS Position

Definition at line 508 of file core_cm3.h.

◆ SCB_AIRCR_ENDIANESS_Pos [6/7]

#define SCB_AIRCR_ENDIANESS_Pos 15U

SCB AIRCR: ENDIANESS Position

Definition at line 568 of file core_cm4.h.

◆ SCB_AIRCR_ENDIANESS_Pos [7/7]

#define SCB_AIRCR_ENDIANESS_Pos 15U

SCB AIRCR: ENDIANESS Position

Definition at line 612 of file core_cm7.h.

◆ SCB_AIRCR_PRIGROUP_Msk [1/4]

#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 509 of file core_sc300.h.

◆ SCB_AIRCR_PRIGROUP_Msk [2/4]

#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 512 of file core_cm3.h.

Referenced by NVIC_DecodePriority(), NVIC_GetPriorityGrouping(), and NVIC_SetPriorityGrouping().

◆ SCB_AIRCR_PRIGROUP_Msk [3/4]

#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 572 of file core_cm4.h.

◆ SCB_AIRCR_PRIGROUP_Msk [4/4]

#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 616 of file core_cm7.h.

◆ SCB_AIRCR_PRIGROUP_Pos [1/4]

#define SCB_AIRCR_PRIGROUP_Pos 8U

SCB AIRCR: PRIGROUP Position

Definition at line 508 of file core_sc300.h.

◆ SCB_AIRCR_PRIGROUP_Pos [2/4]

#define SCB_AIRCR_PRIGROUP_Pos 8U

SCB AIRCR: PRIGROUP Position

Definition at line 511 of file core_cm3.h.

Referenced by NVIC_GetPriorityGrouping().

◆ SCB_AIRCR_PRIGROUP_Pos [3/4]

#define SCB_AIRCR_PRIGROUP_Pos 8U

SCB AIRCR: PRIGROUP Position

Definition at line 571 of file core_cm4.h.

◆ SCB_AIRCR_PRIGROUP_Pos [4/4]

#define SCB_AIRCR_PRIGROUP_Pos 8U

SCB AIRCR: PRIGROUP Position

Definition at line 615 of file core_cm7.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [1/7]

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 457 of file core_cm0.h.

Referenced by NVIC_SystemReset().

◆ SCB_AIRCR_SYSRESETREQ_Msk [2/7]

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 469 of file core_sc000.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [3/7]

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 481 of file core_cm0plus.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [4/7]

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 512 of file core_sc300.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [5/7]

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 515 of file core_cm3.h.

Referenced by NVIC_DecodePriority().

◆ SCB_AIRCR_SYSRESETREQ_Msk [6/7]

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 575 of file core_cm4.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [7/7]

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 619 of file core_cm7.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [1/7]

#define SCB_AIRCR_SYSRESETREQ_Pos 2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 456 of file core_cm0.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [2/7]

#define SCB_AIRCR_SYSRESETREQ_Pos 2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 468 of file core_sc000.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [3/7]

#define SCB_AIRCR_SYSRESETREQ_Pos 2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 480 of file core_cm0plus.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [4/7]

#define SCB_AIRCR_SYSRESETREQ_Pos 2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 511 of file core_sc300.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [5/7]

#define SCB_AIRCR_SYSRESETREQ_Pos 2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 514 of file core_cm3.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [6/7]

#define SCB_AIRCR_SYSRESETREQ_Pos 2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 574 of file core_cm4.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [7/7]

#define SCB_AIRCR_SYSRESETREQ_Pos 2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 618 of file core_cm7.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [1/7]

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 460 of file core_cm0.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [2/7]

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 472 of file core_sc000.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [3/7]

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 484 of file core_cm0plus.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [4/7]

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 515 of file core_sc300.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [5/7]

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 518 of file core_cm3.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [6/7]

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 578 of file core_cm4.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [7/7]

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 622 of file core_cm7.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [1/7]

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 459 of file core_cm0.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [2/7]

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 471 of file core_sc000.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [3/7]

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 483 of file core_cm0plus.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [4/7]

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 514 of file core_sc300.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [5/7]

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 517 of file core_cm3.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [6/7]

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 577 of file core_cm4.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [7/7]

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 621 of file core_cm7.h.

◆ SCB_AIRCR_VECTKEY_Msk [1/7]

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 448 of file core_cm0.h.

◆ SCB_AIRCR_VECTKEY_Msk [2/7]

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 460 of file core_sc000.h.

◆ SCB_AIRCR_VECTKEY_Msk [3/7]

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 472 of file core_cm0plus.h.

◆ SCB_AIRCR_VECTKEY_Msk [4/7]

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 500 of file core_sc300.h.

◆ SCB_AIRCR_VECTKEY_Msk [5/7]

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 503 of file core_cm3.h.

Referenced by NVIC_SetPriorityGrouping().

◆ SCB_AIRCR_VECTKEY_Msk [6/7]

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 563 of file core_cm4.h.

◆ SCB_AIRCR_VECTKEY_Msk [7/7]

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 607 of file core_cm7.h.

◆ SCB_AIRCR_VECTKEY_Pos [1/7]

#define SCB_AIRCR_VECTKEY_Pos 16U

SCB AIRCR: VECTKEY Position

Definition at line 447 of file core_cm0.h.

Referenced by NVIC_SystemReset().

◆ SCB_AIRCR_VECTKEY_Pos [2/7]

#define SCB_AIRCR_VECTKEY_Pos 16U

SCB AIRCR: VECTKEY Position

Definition at line 459 of file core_sc000.h.

◆ SCB_AIRCR_VECTKEY_Pos [3/7]

#define SCB_AIRCR_VECTKEY_Pos 16U

SCB AIRCR: VECTKEY Position

Definition at line 471 of file core_cm0plus.h.

◆ SCB_AIRCR_VECTKEY_Pos [4/7]

#define SCB_AIRCR_VECTKEY_Pos 16U

SCB AIRCR: VECTKEY Position

Definition at line 499 of file core_sc300.h.

◆ SCB_AIRCR_VECTKEY_Pos [5/7]

#define SCB_AIRCR_VECTKEY_Pos 16U

SCB AIRCR: VECTKEY Position

Definition at line 502 of file core_cm3.h.

Referenced by NVIC_DecodePriority(), and NVIC_SetPriorityGrouping().

◆ SCB_AIRCR_VECTKEY_Pos [6/7]

#define SCB_AIRCR_VECTKEY_Pos 16U

SCB AIRCR: VECTKEY Position

Definition at line 562 of file core_cm4.h.

◆ SCB_AIRCR_VECTKEY_Pos [7/7]

#define SCB_AIRCR_VECTKEY_Pos 16U

SCB AIRCR: VECTKEY Position

Definition at line 606 of file core_cm7.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [1/7]

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 451 of file core_cm0.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [2/7]

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 463 of file core_sc000.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [3/7]

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 475 of file core_cm0plus.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [4/7]

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 503 of file core_sc300.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [5/7]

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 506 of file core_cm3.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [6/7]

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 566 of file core_cm4.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [7/7]

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 610 of file core_cm7.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [1/7]

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 450 of file core_cm0.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [2/7]

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 462 of file core_sc000.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [3/7]

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 474 of file core_cm0plus.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [4/7]

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 502 of file core_sc300.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [5/7]

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 505 of file core_cm3.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [6/7]

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 565 of file core_cm4.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [7/7]

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 609 of file core_cm7.h.

◆ SCB_AIRCR_VECTRESET_Msk [1/4]

#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

Definition at line 518 of file core_sc300.h.

◆ SCB_AIRCR_VECTRESET_Msk [2/4]

#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

Definition at line 521 of file core_cm3.h.

◆ SCB_AIRCR_VECTRESET_Msk [3/4]

#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

Definition at line 581 of file core_cm4.h.

◆ SCB_AIRCR_VECTRESET_Msk [4/4]

#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

Definition at line 625 of file core_cm7.h.

◆ SCB_AIRCR_VECTRESET_Pos [1/4]

#define SCB_AIRCR_VECTRESET_Pos 0U

SCB AIRCR: VECTRESET Position

Definition at line 517 of file core_sc300.h.

◆ SCB_AIRCR_VECTRESET_Pos [2/4]

#define SCB_AIRCR_VECTRESET_Pos 0U

SCB AIRCR: VECTRESET Position

Definition at line 520 of file core_cm3.h.

◆ SCB_AIRCR_VECTRESET_Pos [3/4]

#define SCB_AIRCR_VECTRESET_Pos 0U

SCB AIRCR: VECTRESET Position

Definition at line 580 of file core_cm4.h.

◆ SCB_AIRCR_VECTRESET_Pos [4/4]

#define SCB_AIRCR_VECTRESET_Pos 0U

SCB AIRCR: VECTRESET Position

Definition at line 624 of file core_cm7.h.

◆ SCB_CACR_ECCEN_Msk

#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos)

SCB CACR: ECCEN Mask

Definition at line 859 of file core_cm7.h.

◆ SCB_CACR_ECCEN_Pos

#define SCB_CACR_ECCEN_Pos 1U

SCB CACR: ECCEN Position

Definition at line 858 of file core_cm7.h.

◆ SCB_CACR_FORCEWT_Msk

#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos)

SCB CACR: FORCEWT Mask

Definition at line 856 of file core_cm7.h.

◆ SCB_CACR_FORCEWT_Pos

#define SCB_CACR_FORCEWT_Pos 2U

SCB CACR: FORCEWT Position

Definition at line 855 of file core_cm7.h.

◆ SCB_CACR_SIWT_Msk

#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/)

SCB CACR: SIWT Mask

Definition at line 862 of file core_cm7.h.

◆ SCB_CACR_SIWT_Pos

#define SCB_CACR_SIWT_Pos 0U

SCB CACR: SIWT Position

Definition at line 861 of file core_cm7.h.

◆ SCB_CCR_BFHFNMIGN_Msk [1/4]

#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 535 of file core_sc300.h.

◆ SCB_CCR_BFHFNMIGN_Msk [2/4]

#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 538 of file core_cm3.h.

◆ SCB_CCR_BFHFNMIGN_Msk [3/4]

#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 598 of file core_cm4.h.

◆ SCB_CCR_BFHFNMIGN_Msk [4/4]

#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 651 of file core_cm7.h.

◆ SCB_CCR_BFHFNMIGN_Pos [1/4]

#define SCB_CCR_BFHFNMIGN_Pos 8U

SCB CCR: BFHFNMIGN Position

Definition at line 534 of file core_sc300.h.

◆ SCB_CCR_BFHFNMIGN_Pos [2/4]

#define SCB_CCR_BFHFNMIGN_Pos 8U

SCB CCR: BFHFNMIGN Position

Definition at line 537 of file core_cm3.h.

◆ SCB_CCR_BFHFNMIGN_Pos [3/4]

#define SCB_CCR_BFHFNMIGN_Pos 8U

SCB CCR: BFHFNMIGN Position

Definition at line 597 of file core_cm4.h.

◆ SCB_CCR_BFHFNMIGN_Pos [4/4]

#define SCB_CCR_BFHFNMIGN_Pos 8U

SCB CCR: BFHFNMIGN Position

Definition at line 650 of file core_cm7.h.

◆ SCB_CCR_BP_Msk

#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)

SCB CCR: Branch prediction enable bit Mask

Definition at line 639 of file core_cm7.h.

◆ SCB_CCR_BP_Pos

#define SCB_CCR_BP_Pos 18U

SCB CCR: Branch prediction enable bit Position

Definition at line 638 of file core_cm7.h.

◆ SCB_CCR_DC_Msk

#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)

SCB CCR: Cache enable bit Mask

Definition at line 645 of file core_cm7.h.

Referenced by SCB_DisableDCache().

◆ SCB_CCR_DC_Pos

#define SCB_CCR_DC_Pos 16U

SCB CCR: Cache enable bit Position

Definition at line 644 of file core_cm7.h.

◆ SCB_CCR_DIV_0_TRP_Msk [1/4]

#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 538 of file core_sc300.h.

◆ SCB_CCR_DIV_0_TRP_Msk [2/4]

#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 541 of file core_cm3.h.

◆ SCB_CCR_DIV_0_TRP_Msk [3/4]

#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 601 of file core_cm4.h.

◆ SCB_CCR_DIV_0_TRP_Msk [4/4]

#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 654 of file core_cm7.h.

◆ SCB_CCR_DIV_0_TRP_Pos [1/4]

#define SCB_CCR_DIV_0_TRP_Pos 4U

SCB CCR: DIV_0_TRP Position

Definition at line 537 of file core_sc300.h.

◆ SCB_CCR_DIV_0_TRP_Pos [2/4]

#define SCB_CCR_DIV_0_TRP_Pos 4U

SCB CCR: DIV_0_TRP Position

Definition at line 540 of file core_cm3.h.

◆ SCB_CCR_DIV_0_TRP_Pos [3/4]

#define SCB_CCR_DIV_0_TRP_Pos 4U

SCB CCR: DIV_0_TRP Position

Definition at line 600 of file core_cm4.h.

◆ SCB_CCR_DIV_0_TRP_Pos [4/4]

#define SCB_CCR_DIV_0_TRP_Pos 4U

SCB CCR: DIV_0_TRP Position

Definition at line 653 of file core_cm7.h.

◆ SCB_CCR_IC_Msk

#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)

SCB CCR: Instruction cache enable bit Mask

Definition at line 642 of file core_cm7.h.

Referenced by SCB_DisableICache(), and SCB_EnableICache().

◆ SCB_CCR_IC_Pos

#define SCB_CCR_IC_Pos 17U

SCB CCR: Instruction cache enable bit Position

Definition at line 641 of file core_cm7.h.

◆ SCB_CCR_NONBASETHRDENA_Msk [1/4]

#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

Definition at line 547 of file core_sc300.h.

◆ SCB_CCR_NONBASETHRDENA_Msk [2/4]

#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

Definition at line 550 of file core_cm3.h.

◆ SCB_CCR_NONBASETHRDENA_Msk [3/4]

#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

Definition at line 610 of file core_cm4.h.

◆ SCB_CCR_NONBASETHRDENA_Msk [4/4]

#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

Definition at line 663 of file core_cm7.h.

◆ SCB_CCR_NONBASETHRDENA_Pos [1/4]

#define SCB_CCR_NONBASETHRDENA_Pos 0U

SCB CCR: NONBASETHRDENA Position

Definition at line 546 of file core_sc300.h.

◆ SCB_CCR_NONBASETHRDENA_Pos [2/4]

#define SCB_CCR_NONBASETHRDENA_Pos 0U

SCB CCR: NONBASETHRDENA Position

Definition at line 549 of file core_cm3.h.

◆ SCB_CCR_NONBASETHRDENA_Pos [3/4]

#define SCB_CCR_NONBASETHRDENA_Pos 0U

SCB CCR: NONBASETHRDENA Position

Definition at line 609 of file core_cm4.h.

◆ SCB_CCR_NONBASETHRDENA_Pos [4/4]

#define SCB_CCR_NONBASETHRDENA_Pos 0U

SCB CCR: NONBASETHRDENA Position

Definition at line 662 of file core_cm7.h.

◆ SCB_CCR_STKALIGN_Msk [1/7]

#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 474 of file core_cm0.h.

◆ SCB_CCR_STKALIGN_Msk [2/7]

#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 486 of file core_sc000.h.

◆ SCB_CCR_STKALIGN_Msk [3/7]

#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 498 of file core_cm0plus.h.

◆ SCB_CCR_STKALIGN_Msk [4/7]

#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 532 of file core_sc300.h.

◆ SCB_CCR_STKALIGN_Msk [5/7]

#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 535 of file core_cm3.h.

◆ SCB_CCR_STKALIGN_Msk [6/7]

#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 595 of file core_cm4.h.

◆ SCB_CCR_STKALIGN_Msk [7/7]

#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 648 of file core_cm7.h.

◆ SCB_CCR_STKALIGN_Pos [1/7]

#define SCB_CCR_STKALIGN_Pos 9U

SCB CCR: STKALIGN Position

Definition at line 473 of file core_cm0.h.

◆ SCB_CCR_STKALIGN_Pos [2/7]

#define SCB_CCR_STKALIGN_Pos 9U

SCB CCR: STKALIGN Position

Definition at line 485 of file core_sc000.h.

◆ SCB_CCR_STKALIGN_Pos [3/7]

#define SCB_CCR_STKALIGN_Pos 9U

SCB CCR: STKALIGN Position

Definition at line 497 of file core_cm0plus.h.

◆ SCB_CCR_STKALIGN_Pos [4/7]

#define SCB_CCR_STKALIGN_Pos 9U

SCB CCR: STKALIGN Position

Definition at line 531 of file core_sc300.h.

◆ SCB_CCR_STKALIGN_Pos [5/7]

#define SCB_CCR_STKALIGN_Pos 9U

SCB CCR: STKALIGN Position

Definition at line 534 of file core_cm3.h.

◆ SCB_CCR_STKALIGN_Pos [6/7]

#define SCB_CCR_STKALIGN_Pos 9U

SCB CCR: STKALIGN Position

Definition at line 594 of file core_cm4.h.

◆ SCB_CCR_STKALIGN_Pos [7/7]

#define SCB_CCR_STKALIGN_Pos 9U

SCB CCR: STKALIGN Position

Definition at line 647 of file core_cm7.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [1/7]

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 477 of file core_cm0.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [2/7]

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 489 of file core_sc000.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [3/7]

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 501 of file core_cm0plus.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [4/7]

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 541 of file core_sc300.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [5/7]

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 544 of file core_cm3.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [6/7]

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 604 of file core_cm4.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [7/7]

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 657 of file core_cm7.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [1/7]

#define SCB_CCR_UNALIGN_TRP_Pos 3U

SCB CCR: UNALIGN_TRP Position

Definition at line 476 of file core_cm0.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [2/7]

#define SCB_CCR_UNALIGN_TRP_Pos 3U

SCB CCR: UNALIGN_TRP Position

Definition at line 488 of file core_sc000.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [3/7]

#define SCB_CCR_UNALIGN_TRP_Pos 3U

SCB CCR: UNALIGN_TRP Position

Definition at line 500 of file core_cm0plus.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [4/7]

#define SCB_CCR_UNALIGN_TRP_Pos 3U

SCB CCR: UNALIGN_TRP Position

Definition at line 540 of file core_sc300.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [5/7]

#define SCB_CCR_UNALIGN_TRP_Pos 3U

SCB CCR: UNALIGN_TRP Position

Definition at line 543 of file core_cm3.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [6/7]

#define SCB_CCR_UNALIGN_TRP_Pos 3U

SCB CCR: UNALIGN_TRP Position

Definition at line 603 of file core_cm4.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [7/7]

#define SCB_CCR_UNALIGN_TRP_Pos 3U

SCB CCR: UNALIGN_TRP Position

Definition at line 656 of file core_cm7.h.

◆ SCB_CCR_USERSETMPEND_Msk [1/4]

#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 544 of file core_sc300.h.

◆ SCB_CCR_USERSETMPEND_Msk [2/4]

#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 547 of file core_cm3.h.

◆ SCB_CCR_USERSETMPEND_Msk [3/4]

#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 607 of file core_cm4.h.

◆ SCB_CCR_USERSETMPEND_Msk [4/4]

#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 660 of file core_cm7.h.

◆ SCB_CCR_USERSETMPEND_Pos [1/4]

#define SCB_CCR_USERSETMPEND_Pos 1U

SCB CCR: USERSETMPEND Position

Definition at line 543 of file core_sc300.h.

◆ SCB_CCR_USERSETMPEND_Pos [2/4]

#define SCB_CCR_USERSETMPEND_Pos 1U

SCB CCR: USERSETMPEND Position

Definition at line 546 of file core_cm3.h.

◆ SCB_CCR_USERSETMPEND_Pos [3/4]

#define SCB_CCR_USERSETMPEND_Pos 1U

SCB CCR: USERSETMPEND Position

Definition at line 606 of file core_cm4.h.

◆ SCB_CCR_USERSETMPEND_Pos [4/4]

#define SCB_CCR_USERSETMPEND_Pos 1U

SCB CCR: USERSETMPEND Position

Definition at line 659 of file core_cm7.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk

#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

Definition at line 784 of file core_cm7.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos

#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U

SCB CCSIDR: Associativity Position

Definition at line 783 of file core_cm7.h.

◆ SCB_CCSIDR_LINESIZE_Msk

#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

Definition at line 787 of file core_cm7.h.

◆ SCB_CCSIDR_LINESIZE_Pos

#define SCB_CCSIDR_LINESIZE_Pos 0U

SCB CCSIDR: LineSize Position

Definition at line 786 of file core_cm7.h.

◆ SCB_CCSIDR_NUMSETS_Msk

#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

Definition at line 781 of file core_cm7.h.

◆ SCB_CCSIDR_NUMSETS_Pos

#define SCB_CCSIDR_NUMSETS_Pos 13U

SCB CCSIDR: NumSets Position

Definition at line 780 of file core_cm7.h.

◆ SCB_CCSIDR_RA_Msk

#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

Definition at line 775 of file core_cm7.h.

◆ SCB_CCSIDR_RA_Pos

#define SCB_CCSIDR_RA_Pos 29U

SCB CCSIDR: RA Position

Definition at line 774 of file core_cm7.h.

◆ SCB_CCSIDR_WA_Msk

#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

Definition at line 778 of file core_cm7.h.

◆ SCB_CCSIDR_WA_Pos

#define SCB_CCSIDR_WA_Pos 28U

SCB CCSIDR: WA Position

Definition at line 777 of file core_cm7.h.

◆ SCB_CCSIDR_WB_Msk

#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

Definition at line 772 of file core_cm7.h.

◆ SCB_CCSIDR_WB_Pos

#define SCB_CCSIDR_WB_Pos 30U

SCB CCSIDR: WB Position

Definition at line 771 of file core_cm7.h.

◆ SCB_CCSIDR_WT_Msk

#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

Definition at line 769 of file core_cm7.h.

◆ SCB_CCSIDR_WT_Pos

#define SCB_CCSIDR_WT_Pos 31U

SCB CCSIDR: WT Position

Definition at line 768 of file core_cm7.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [1/4]

#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 597 of file core_sc300.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [2/4]

#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 600 of file core_cm3.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [3/4]

#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 660 of file core_cm4.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [4/4]

#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 713 of file core_cm7.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [1/4]

#define SCB_CFSR_BUSFAULTSR_Pos 8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 596 of file core_sc300.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [2/4]

#define SCB_CFSR_BUSFAULTSR_Pos 8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 599 of file core_cm3.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [3/4]

#define SCB_CFSR_BUSFAULTSR_Pos 8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 659 of file core_cm4.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [4/4]

#define SCB_CFSR_BUSFAULTSR_Pos 8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 712 of file core_cm7.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [1/4]

#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 600 of file core_sc300.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [2/4]

#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 603 of file core_cm3.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [3/4]

#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 663 of file core_cm4.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [4/4]

#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 716 of file core_cm7.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [1/4]

#define SCB_CFSR_MEMFAULTSR_Pos 0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 599 of file core_sc300.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [2/4]

#define SCB_CFSR_MEMFAULTSR_Pos 0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 602 of file core_cm3.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [3/4]

#define SCB_CFSR_MEMFAULTSR_Pos 0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 662 of file core_cm4.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [4/4]

#define SCB_CFSR_MEMFAULTSR_Pos 0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 715 of file core_cm7.h.

◆ SCB_CFSR_USGFAULTSR_Msk [1/4]

#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 594 of file core_sc300.h.

◆ SCB_CFSR_USGFAULTSR_Msk [2/4]

#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 597 of file core_cm3.h.

◆ SCB_CFSR_USGFAULTSR_Msk [3/4]

#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 657 of file core_cm4.h.

◆ SCB_CFSR_USGFAULTSR_Msk [4/4]

#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 710 of file core_cm7.h.

◆ SCB_CFSR_USGFAULTSR_Pos [1/4]

#define SCB_CFSR_USGFAULTSR_Pos 16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 593 of file core_sc300.h.

◆ SCB_CFSR_USGFAULTSR_Pos [2/4]

#define SCB_CFSR_USGFAULTSR_Pos 16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 596 of file core_cm3.h.

◆ SCB_CFSR_USGFAULTSR_Pos [3/4]

#define SCB_CFSR_USGFAULTSR_Pos 16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 656 of file core_cm4.h.

◆ SCB_CFSR_USGFAULTSR_Pos [4/4]

#define SCB_CFSR_USGFAULTSR_Pos 16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 709 of file core_cm7.h.

◆ SCB_CLIDR_LOC_Msk

#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

Definition at line 749 of file core_cm7.h.

◆ SCB_CLIDR_LOC_Pos

#define SCB_CLIDR_LOC_Pos 24U

SCB CLIDR: LoC Position

Definition at line 748 of file core_cm7.h.

◆ SCB_CLIDR_LOUU_Msk

#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

Definition at line 746 of file core_cm7.h.

◆ SCB_CLIDR_LOUU_Pos

#define SCB_CLIDR_LOUU_Pos 27U

SCB CLIDR: LoUU Position

Definition at line 745 of file core_cm7.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [1/7]

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 410 of file core_cm0.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [2/7]

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 418 of file core_sc000.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [3/7]

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 428 of file core_cm0plus.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [4/7]

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 450 of file core_cm3.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [5/7]

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 452 of file core_sc300.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [6/7]

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 518 of file core_cm4.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [7/7]

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 562 of file core_cm7.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [1/7]

#define SCB_CPUID_ARCHITECTURE_Pos 16U

SCB CPUID: ARCHITECTURE Position

Definition at line 409 of file core_cm0.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [2/7]

#define SCB_CPUID_ARCHITECTURE_Pos 16U

SCB CPUID: ARCHITECTURE Position

Definition at line 417 of file core_sc000.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [3/7]

#define SCB_CPUID_ARCHITECTURE_Pos 16U

SCB CPUID: ARCHITECTURE Position

Definition at line 427 of file core_cm0plus.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [4/7]

#define SCB_CPUID_ARCHITECTURE_Pos 16U

SCB CPUID: ARCHITECTURE Position

Definition at line 449 of file core_cm3.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [5/7]

#define SCB_CPUID_ARCHITECTURE_Pos 16U

SCB CPUID: ARCHITECTURE Position

Definition at line 451 of file core_sc300.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [6/7]

#define SCB_CPUID_ARCHITECTURE_Pos 16U

SCB CPUID: ARCHITECTURE Position

Definition at line 517 of file core_cm4.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [7/7]

#define SCB_CPUID_ARCHITECTURE_Pos 16U

SCB CPUID: ARCHITECTURE Position

Definition at line 561 of file core_cm7.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [1/7]

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 404 of file core_cm0.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [2/7]

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 412 of file core_sc000.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [3/7]

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 422 of file core_cm0plus.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [4/7]

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 444 of file core_cm3.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [5/7]

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 446 of file core_sc300.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [6/7]

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 512 of file core_cm4.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [7/7]

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 556 of file core_cm7.h.