52#define SPI0_CLK_PORT (-1)
55#define SPI0_CLK_PIN (-1)
57#if SPI0_CLK_PORT >= 0 && SPI0_CLK_PIN < 0 || \
58 SPI0_CLK_PORT < 0 && SPI0_CLK_PIN >= 0
59#error Both SPI0_CLK_PORT and SPI0_CLK_PIN must be valid or invalid
63#define SPI0_TX_PORT (-1)
66#define SPI0_TX_PIN (-1)
68#if SPI0_TX_PORT >= 0 && SPI0_TX_PIN < 0 || \
69 SPI0_TX_PORT < 0 && SPI0_TX_PIN >= 0
70#error Both SPI0_TX_PORT and SPI0_TX_PIN must be valid or invalid
74#define SPI0_RX_PORT (-1)
77#define SPI0_RX_PIN (-1)
79#if SPI0_RX_PORT >= 0 && SPI0_RX_PIN < 0 || \
80 SPI0_RX_PORT < 0 && SPI0_RX_PIN >= 0
81#error Both SPI0_RX_PORT and SPI0_RX_PIN must be valid or invalid
89#if SPI0_CLK_PORT >= 0 || SPI0_TX_PORT >= 0 || SPI0_RX_PORT >= 0
91#if SPI0_CLK_PORT < 0 || SPI0_TX_PORT < 0 || SPI0_RX_PORT < 0
92#error Some SPI0 pad definitions are invalid
94#define SPI0_PADS_VALID
99#define SPI1_CLK_PORT (-1)
102#define SPI1_CLK_PIN (-1)
104#if SPI1_CLK_PORT >= 0 && SPI1_CLK_PIN < 0 || \
105 SPI1_CLK_PORT < 0 && SPI1_CLK_PIN >= 0
106#error Both SPI1_CLK_PORT and SPI1_CLK_PIN must be valid or invalid
110#define SPI1_TX_PORT (-1)
113#define SPI1_TX_PIN (-1)
115#if SPI1_TX_PORT >= 0 && SPI1_TX_PIN < 0 || \
116 SPI1_TX_PORT < 0 && SPI1_TX_PIN >= 0
117#error Both SPI1_TX_PORT and SPI1_TX_PIN must be valid or invalid
121#define SPI1_RX_PORT (-1)
124#define SPI1_RX_PIN (-1)
126#if SPI1_RX_PORT >= 0 && SPI1_RX_PIN < 0 || \
127 SPI1_RX_PORT < 0 && SPI1_RX_PIN >= 0
128#error Both SPI1_RX_PORT and SPI1_RX_PIN must be valid or invalid
132#if SPI1_CLK_PORT >= 0 || SPI1_TX_PORT >= 0 || SPI1_RX_PORT >= 0
134#if SPI1_CLK_PORT < 0 || SPI1_TX_PORT < 0 || SPI1_RX_PORT < 0
135#error Some SPI1 pad definitions are invalid
137#define SPI1_PADS_VALID
140#ifdef SPI_DEFAULT_INSTANCE
141#if SPI_DEFAULT_INSTANCE == 0
142#ifndef SPI0_PADS_VALID
143#error SPI_DEFAULT_INSTANCE is set to SPI0, but its pads are not valid
145#elif SPI_DEFAULT_INSTANCE == 1
146#ifndef SPI1_PADS_VALID
147#error SPI_DEFAULT_INSTANCE is set to SPI1, but its pads are not valid
152#if (SPI0_CPRS_CPSDVSR & 1) == 1 || SPI0_CPRS_CPSDVSR < 2 || SPI0_CPRS_CPSDVSR > 254
153#error SPI0_CPRS_CPSDVSR must be an even number between 2 and 254
156#if (SPI1_CPRS_CPSDVSR & 1) == 1 || SPI1_CPRS_CPSDVSR < 2 || SPI1_CPRS_CPSDVSR > 254
157#error SPI1_CPRS_CPSDVSR must be an even number between 2 and 254
164#define SSI_SYS_CLOCK SYS_CTRL_SYS_CLOCK
172 uint32_t ioc_ssirxd_ssi;
173 uint32_t ioc_pxx_sel_ssi_clkout;
174 uint32_t ioc_pxx_sel_ssi_txd;
175 uint8_t ssi_cprs_cpsdvsr;
181static const spi_regs_t spi_regs[SSI_INSTANCE_COUNT] = {
185 .ioc_pxx_sel_ssi_clkout = IOC_PXX_SEL_SSI0_CLKOUT,
186 .ioc_pxx_sel_ssi_txd = IOC_PXX_SEL_SSI0_TXD,
187 .ssi_cprs_cpsdvsr = SPI0_CPRS_CPSDVSR,
188 .clk = { SPI0_CLK_PORT, SPI0_CLK_PIN },
189 .tx = { SPI0_TX_PORT, SPI0_TX_PIN },
190 .rx = { SPI0_RX_PORT, SPI0_RX_PIN }
194 .ioc_pxx_sel_ssi_clkout = IOC_PXX_SEL_SSI1_CLKOUT,
195 .ioc_pxx_sel_ssi_txd = IOC_PXX_SEL_SSI1_TXD,
196 .ssi_cprs_cpsdvsr = SPI1_CPRS_CPSDVSR,
197 .clk = { SPI1_CLK_PORT, SPI1_CLK_PIN },
198 .tx = { SPI1_TX_PORT, SPI1_TX_PIN },
199 .rx = { SPI1_RX_PORT, SPI1_RX_PIN }
204#ifdef SPI_DEFAULT_INSTANCE
215 const spi_regs_t *regs;
217 if(spi >= SSI_INSTANCE_COUNT) {
221 regs = &spi_regs[spi];
223 if(regs->clk.port < 0) {
236 REG(regs->base +
SSI_CC) = 0;
241 regs->ioc_pxx_sel_ssi_clkout);
244 regs->ioc_pxx_sel_ssi_txd);
245 REG(regs->ioc_ssirxd_ssi) = (regs->rx.port * 8) + regs->rx.pin;
261 REG(regs->base +
SSI_CPSR) = regs->ssi_cprs_cpsdvsr;
279 if(spi >= SSI_INSTANCE_COUNT) {
288 if(spi >= SSI_INSTANCE_COUNT) {
296 uint32_t frame_format,
297 uint32_t clock_polarity,
298 uint32_t clock_phase,
301 const spi_regs_t *regs;
303 if(spi >= SSI_INSTANCE_COUNT) {
307 regs = &spi_regs[spi];
313 REG(regs->base +
SSI_CR0) = clock_phase |
325 const spi_regs_t *regs;
329 if(spi >= SSI_INSTANCE_COUNT) {
333 regs = &spi_regs[spi];
342 div = (uint64_t)regs->ssi_cprs_cpsdvsr * freq;
343 scr = (SSI_SYS_CLOCK + div - 1) / div;
344 scr = MIN(MAX(scr, 1), 256) - 1;
346 REG(regs->base +
SSI_CR0) = (REG(regs->base +
SSI_CR0) & ~SSI_CR0_SCR_M) |
Default definitions of C compiler quirk work-arounds.
Header file with register and macro declarations for the cc2538 GPIO module.
#define GPIO_PIN_MASK(PIN)
Converts a pin number to a pin mask.
#define GPIO_PERIPHERAL_CONTROL(PORT_BASE, PIN_MASK)
Configure the pin to be under peripheral control with PIN_MASK of port with PORT_BASE.
#define GPIO_SOFTWARE_CONTROL(PORT_BASE, PIN_MASK)
Configure the pin to be software controlled with PIN_MASK of port with PORT_BASE.
#define GPIO_PORT_TO_BASE(PORT)
Converts a port number to the port base address.
#define GPIO_SET_PIN(PORT_BASE, PIN_MASK)
Set pins with PIN_MASK of port with PORT_BASE high.
#define GPIO_SET_OUTPUT(PORT_BASE, PIN_MASK)
Set pins with PIN_MASK of port with PORT_BASE to output.
void ioc_set_sel(uint8_t port, uint8_t pin, uint8_t sel)
Function select for Port:Pin.
#define IOC_SSIRXD_SSI0
SSI0 RX.
void ioc_set_over(uint8_t port, uint8_t pin, uint8_t over)
Set Port:Pin override function.
#define IOC_OVERRIDE_DIS
Override Disabled.
#define IOC_SSIRXD_SSI1
SSI1 RX.
#define SSI1_BASE
Base address for SSI1.
void spix_set_mode(uint8_t spi, uint32_t frame_format, uint32_t clock_polarity, uint32_t clock_phase, uint32_t data_size)
Configure the SPI data and clock polarity and the data size for the instance given.
#define SSI_CR1
Control register 1.
#define SSI_CR0
Control register 0.
#define SSI_CC
Clock configuration.
void spix_enable(uint8_t spi)
Enables the SPI peripheral for the instance given.
void spix_init(uint8_t spi)
Initialize the SPI bus for the instance given.
void spix_cs_init(uint8_t port, uint8_t pin)
Configure a GPIO to be the chip select pin.
#define SSI_CR0_SCR_S
Serial clock rate shift.
#define SSI_CR0_SPH
Serial clock phase (H)
#define SSI0_BASE
Base address for SSI0.
void spix_disable(uint8_t spi)
Disables the SPI peripheral for the instance given.
#define SSI_CPSR
Clock divider.
void spix_set_clock_freq(uint8_t spi, uint32_t freq)
Sets the SPI clock frequency of the given SSI instance.
#define SSI_CR0_SPO
Serial clock phase (O)
#define SSI_CR1_SSE
Synchronous serial port enable.
#define SYS_CTRL_RCGCSSI
SSI[1:0] clocks - active mode.
Header file with declarations for the I/O Control module.
Header file with register manipulation macro definitions.
Header file for the cc2538 SPI driver, including macros for the implementation of the low-level SPI p...
Header file for the cc2538 Synchronous Serial Interface.
Header file for the cc2538 System Control driver.