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SYS_CTRL_CLOCK_CTRL register
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#define | SYS_CTRL_32MHZ 32000000 |
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#define | SYS_CTRL_16MHZ 16000000 |
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#define | SYS_CTRL_8MHZ 8000000 |
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#define | SYS_CTRL_4MHZ 4000000 |
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#define | SYS_CTRL_2MHZ 2000000 |
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#define | SYS_CTRL_1MHZ 1000000 |
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#define | SYS_CTRL_500KHZ 500000 |
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#define | SYS_CTRL_250KHZ 250000 |
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#define | SYS_CTRL_CLOCK_CTRL 0x400D2000 |
| Clock control register.
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#define | SYS_CTRL_CLOCK_STA 0x400D2004 |
| Clock status register.
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#define | SYS_CTRL_RCGCGPT 0x400D2008 |
| GPT[3:0] clocks - active mode.
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#define | SYS_CTRL_SCGCGPT 0x400D200C |
| GPT[3:0] clocks - sleep mode.
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#define | SYS_CTRL_DCGCGPT 0x400D2010 |
| GPT[3:0] clocks - PM0.
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#define | SYS_CTRL_SRGPT 0x400D2014 |
| GPT[3:0] reset control.
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#define | SYS_CTRL_RCGCSSI 0x400D2018 |
| SSI[1:0] clocks - active mode.
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#define | SYS_CTRL_SCGCSSI 0x400D201C |
| SSI[1:0] clocks - sleep mode.
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#define | SYS_CTRL_DCGCSSI 0x400D2020 |
| SSI[1:0] clocks - PM0 mode.
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#define | SYS_CTRL_SRSSI 0x400D2024 |
| SSI[1:0] reset control.
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#define | SYS_CTRL_RCGCUART 0x400D2028 |
| UART[1:0] clocks - active mode.
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#define | SYS_CTRL_SCGCUART 0x400D202C |
| UART[1:0] clocks - sleep mode.
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#define | SYS_CTRL_DCGCUART 0x400D2030 |
| UART[1:0] clocks - PM0.
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#define | SYS_CTRL_SRUART 0x400D2034 |
| UART[1:0] reset control.
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#define | SYS_CTRL_RCGCI2C 0x400D2038 |
| I2C clocks - active mode.
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#define | SYS_CTRL_SCGCI2C 0x400D203C |
| I2C clocks - sleep mode.
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#define | SYS_CTRL_DCGCI2C 0x400D2040 |
| I2C clocks - PM0.
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#define | SYS_CTRL_SRI2C 0x400D2044 |
| I2C clocks - reset control.
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#define | SYS_CTRL_RCGCSEC 0x400D2048 |
| Sec Mod clocks - active mode.
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#define | SYS_CTRL_SCGCSEC 0x400D204C |
| Sec Mod clocks - sleep mode.
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#define | SYS_CTRL_DCGCSEC 0x400D2050 |
| Sec Mod clocks - PM0.
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#define | SYS_CTRL_SRSEC 0x400D2054 |
| Sec Mod reset control.
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#define | SYS_CTRL_PMCTL 0x400D2058 |
| Power Mode Control.
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#define | SYS_CTRL_SRCRC 0x400D205C |
| CRC on state retention.
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#define | SYS_CTRL_PWRDBG 0x400D2074 |
| Power debug register.
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#define | SYS_CTRL_CLD 0x400D2080 |
| clock loss detection feature
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#define | SYS_CTRL_IWE 0x400D2094 |
| interrupt wake-up.
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#define | SYS_CTRL_I_MAP 0x400D2098 |
| Interrupt map select.
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#define | SYS_CTRL_RCGCRFC 0x400D20A8 |
| RF Core clocks - active mode.
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#define | SYS_CTRL_SCGCRFC 0x400D20AC |
| RF Core clocks - Sleep mode.
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#define | SYS_CTRL_DCGCRFC 0x400D20B0 |
| RF Core clocks - PM0.
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#define | SYS_CTRL_EMUOVR 0x400D20B4 |
| Emulator override.
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#define | SYS_CTRL_CLOCK_CTRL_OSC32K_CALDIS 0x02000000 |
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#define | SYS_CTRL_CLOCK_CTRL_OSC32K 0x01000000 |
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#define | SYS_CTRL_CLOCK_CTRL_AMP_DET 0x00200000 |
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#define | SYS_CTRL_CLOCK_CTRL_OSC_PD 0x00020000 |
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#define | SYS_CTRL_CLOCK_CTRL_OSC 0x00010000 |
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#define | SYS_CTRL_CLOCK_CTRL_IO_DIV 0x00000700 |
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#define | SYS_CTRL_CLOCK_CTRL_SYS_DIV 0x00000007 |
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#define | SYS_CTRL_CLOCK_STA_SYNC_32K 0x04000000 |
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#define | SYS_CTRL_CLOCK_STA_OSC32K_CALDIS 0x02000000 |
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#define | SYS_CTRL_CLOCK_STA_OSC32K 0x01000000 |
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#define | SYS_CTRL_CLOCK_STA_RST 0x00C00000 |
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#define | SYS_CTRL_CLOCK_STA_RST_S 22 |
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#define | SYS_CTRL_CLOCK_STA_RST_POR 0 |
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#define | SYS_CTRL_CLOCK_STA_RST_EXT 1 |
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#define | SYS_CTRL_CLOCK_STA_RST_WDT 2 |
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#define | SYS_CTRL_CLOCK_STA_RST_CLD_SW 3 |
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#define | SYS_CTRL_CLOCK_STA_SOURCE_CHANGE 0x00100000 |
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#define | SYS_CTRL_CLOCK_STA_XOSC_STB 0x00080000 |
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#define | SYS_CTRL_CLOCK_STA_HSOSC_STB 0x00040000 |
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#define | SYS_CTRL_CLOCK_STA_OSC_PD 0x00020000 |
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#define | SYS_CTRL_CLOCK_STA_OSC 0x00010000 |
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#define | SYS_CTRL_CLOCK_STA_IO_DIV 0x00000700 |
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#define | SYS_CTRL_CLOCK_STA_RTCLK_FREQ 0x00000018 |
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#define | SYS_CTRL_CLOCK_STA_SYS_DIV 0x00000007 |
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#define | SYS_CTRL_RCGCGPT_GPT3 0x00000008 |
| GPT3 clock enable, CPU running.
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#define | SYS_CTRL_RCGCGPT_GPT2 0x00000004 |
| GPT2 clock enable, CPU running.
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#define | SYS_CTRL_RCGCGPT_GPT1 0x00000002 |
| GPT1 clock enable, CPU running.
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#define | SYS_CTRL_RCGCGPT_GPT0 0x00000001 |
| GPT0 clock enable, CPU running.
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#define | SYS_CTRL_SCGCGPT_GPT3 0x00000008 |
| GPT3 clock enable, CPU IDLE.
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#define | SYS_CTRL_SCGCGPT_GPT2 0x00000004 |
| GPT2 clock enable, CPU IDLE.
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#define | SYS_CTRL_SCGCGPT_GPT1 0x00000002 |
| GPT1 clock enable, CPU IDLE.
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#define | SYS_CTRL_SCGCGPT_GPT0 0x00000001 |
| GPT0 clock enable, CPU IDLE.
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#define | SYS_CTRL_DCGCGPT_GPT3 0x00000008 |
| GPT3 clock enable, PM0.
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#define | SYS_CTRL_DCGCGPT_GPT2 0x00000004 |
| GPT2 clock enable, PM0.
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#define | SYS_CTRL_DCGCGPT_GPT1 0x00000002 |
| GPT1 clock enable, PM0.
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#define | SYS_CTRL_DCGCGPT_GPT0 0x00000001 |
| GPT0 clock enable, PM0.
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#define | SYS_CTRL_SRGPT_GPT3 0x00000008 |
| GPT3 is reset.
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#define | SYS_CTRL_SRGPT_GPT2 0x00000004 |
| GPT2 is reset.
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#define | SYS_CTRL_SRGPT_GPT1 0x00000002 |
| GPT1 is reset.
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#define | SYS_CTRL_SRGPT_GPT0 0x00000001 |
| GPT0 is reset.
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#define | SYS_CTRL_RCGCSEC_AES 0x00000002 |
| AES clock enable, CPU running.
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#define | SYS_CTRL_RCGCSEC_PKA 0x00000001 |
| PKA clock enable, CPU running.
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#define | SYS_CTRL_SCGCSEC_AES 0x00000002 |
| AES clock enable, CPU IDLE.
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#define | SYS_CTRL_SCGCSEC_PKA 0x00000001 |
| PKA clock enable, CPU IDLE.
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#define | SYS_CTRL_DCGCSEC_AES 0x00000002 |
| AES clock enable, PM0.
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#define | SYS_CTRL_DCGCSEC_PKA 0x00000001 |
| PKA clock enable, PM0.
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#define | SYS_CTRL_SRSEC_AES 0x00000002 |
| AES is reset.
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#define | SYS_CTRL_SRSEC_PKA 0x00000001 |
| PKA is reset.
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#define | SYS_CTRL_PWRDBG_FORCE_WARM_RESET 0x00000008 |
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#define | SYS_CTRL_CLOCK_CTRL_SYS_DIV_32MHZ 0x00000000 |
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#define | SYS_CTRL_CLOCK_CTRL_SYS_DIV_16MHZ 0x00000001 |
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#define | SYS_CTRL_CLOCK_CTRL_SYS_DIV_8MHZ 0x00000002 |
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#define | SYS_CTRL_CLOCK_CTRL_SYS_DIV_4MHZ 0x00000003 |
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#define | SYS_CTRL_CLOCK_CTRL_SYS_DIV_2MHZ 0x00000004 |
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#define | SYS_CTRL_CLOCK_CTRL_SYS_DIV_1MHZ 0x00000005 |
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#define | SYS_CTRL_CLOCK_CTRL_SYS_DIV_500KHZ 0x00000006 |
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#define | SYS_CTRL_CLOCK_CTRL_SYS_DIV_250KHZ 0x00000007 |
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#define | SYS_CTRL_CLOCK_CTRL_IO_DIV_32MHZ 0x00000000 |
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#define | SYS_CTRL_CLOCK_CTRL_IO_DIV_16MHZ 0x00000100 |
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#define | SYS_CTRL_CLOCK_CTRL_IO_DIV_8MHZ 0x00000200 |
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#define | SYS_CTRL_CLOCK_CTRL_IO_DIV_4MHZ 0x00000300 |
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#define | SYS_CTRL_CLOCK_CTRL_IO_DIV_2MHZ 0x00000400 |
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#define | SYS_CTRL_CLOCK_CTRL_IO_DIV_1MHZ 0x00000500 |
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#define | SYS_CTRL_CLOCK_CTRL_IO_DIV_500KHZ 0x00000600 |
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#define | SYS_CTRL_CLOCK_CTRL_IO_DIV_250KHZ 0x00000700 |
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#define | SYS_CTRL_RCGCUART_UART1 0x00000002 |
| UART1 Clock, CPU running.
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#define | SYS_CTRL_RCGCUART_UART0 0x00000001 |
| UART0 Clock, CPU running.
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#define | SYS_CTRL_DCGCUART_UART1 0x00000002 |
| UART1 Clock, PM0.
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#define | SYS_CTRL_DCGCUART_UART0 0x00000001 |
| UART0 Clock, PM0.
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#define | SYS_CTRL_SCGCUART_UART1 0x00000002 |
| UART1 Clock, CPU IDLE.
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#define | SYS_CTRL_SCGCUART_UART0 0x00000001 |
| UART0 Clock, CPU IDLE.
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#define | SYS_CTRL_SRUART_UART1 0x00000002 |
| UART1 module is reset.
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#define | SYS_CTRL_SRUART_UART0 0x00000001 |
| UART0 module is reset
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#define | SYS_CTRL_PMCTL_PM3 0x00000003 |
| PM3.
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#define | SYS_CTRL_PMCTL_PM2 0x00000002 |
| PM2.
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#define | SYS_CTRL_PMCTL_PM1 0x00000001 |
| PM1.
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#define | SYS_CTRL_PMCTL_PM0 0x00000000 |
| PM0.
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Prefer the crystal oscillator for time accuracy, and the RC oscillator for cost and power consumption
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#define | SYS_CTRL_OSC32K_USE_XTAL 0 |
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#define | SYS_CTRL_SYS_DIV SYS_CTRL_CLOCK_CTRL_SYS_DIV_16MHZ |
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#define | SYS_CTRL_IO_DIV SYS_CTRL_CLOCK_CTRL_IO_DIV_16MHZ |
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#define | SYS_CTRL_SYS_CLOCK (SYS_CTRL_32MHZ >> SYS_CTRL_SYS_DIV) |
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#define | SYS_CTRL_IO_CLOCK (SYS_CTRL_32MHZ >> (SYS_CTRL_IO_DIV >> 8)) |
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