Contiki-NG
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Driver for the cc2538 System Control Module. More...
Files | |
file | sys-ctrl.c |
Implementation of the cc2538 System Control driver. | |
file | sys-ctrl.h |
Header file for the cc2538 System Control driver. | |
Definitions of Sys Ctrl registers | |
#define | SYS_CTRL_CLOCK_CTRL 0x400D2000 |
Clock control register. | |
#define | SYS_CTRL_CLOCK_STA 0x400D2004 |
Clock status register. | |
#define | SYS_CTRL_RCGCGPT 0x400D2008 |
GPT[3:0] clocks - active mode. | |
#define | SYS_CTRL_SCGCGPT 0x400D200C |
GPT[3:0] clocks - sleep mode. | |
#define | SYS_CTRL_DCGCGPT 0x400D2010 |
GPT[3:0] clocks - PM0. | |
#define | SYS_CTRL_SRGPT 0x400D2014 |
GPT[3:0] reset control. | |
#define | SYS_CTRL_RCGCSSI 0x400D2018 |
SSI[1:0] clocks - active mode. | |
#define | SYS_CTRL_SCGCSSI 0x400D201C |
SSI[1:0] clocks - sleep mode. | |
#define | SYS_CTRL_DCGCSSI 0x400D2020 |
SSI[1:0] clocks - PM0 mode. | |
#define | SYS_CTRL_SRSSI 0x400D2024 |
SSI[1:0] reset control. | |
#define | SYS_CTRL_RCGCUART 0x400D2028 |
UART[1:0] clocks - active mode. | |
#define | SYS_CTRL_SCGCUART 0x400D202C |
UART[1:0] clocks - sleep mode. | |
#define | SYS_CTRL_DCGCUART 0x400D2030 |
UART[1:0] clocks - PM0. | |
#define | SYS_CTRL_SRUART 0x400D2034 |
UART[1:0] reset control. | |
#define | SYS_CTRL_RCGCI2C 0x400D2038 |
I2C clocks - active mode. | |
#define | SYS_CTRL_SCGCI2C 0x400D203C |
I2C clocks - sleep mode. | |
#define | SYS_CTRL_DCGCI2C 0x400D2040 |
I2C clocks - PM0. | |
#define | SYS_CTRL_SRI2C 0x400D2044 |
I2C clocks - reset control. | |
#define | SYS_CTRL_RCGCSEC 0x400D2048 |
Sec Mod clocks - active mode. | |
#define | SYS_CTRL_SCGCSEC 0x400D204C |
Sec Mod clocks - sleep mode. | |
#define | SYS_CTRL_DCGCSEC 0x400D2050 |
Sec Mod clocks - PM0. | |
#define | SYS_CTRL_SRSEC 0x400D2054 |
Sec Mod reset control. | |
#define | SYS_CTRL_PMCTL 0x400D2058 |
Power Mode Control. | |
#define | SYS_CTRL_SRCRC 0x400D205C |
CRC on state retention. | |
#define | SYS_CTRL_PWRDBG 0x400D2074 |
Power debug register. | |
#define | SYS_CTRL_CLD 0x400D2080 |
clock loss detection feature | |
#define | SYS_CTRL_IWE 0x400D2094 |
interrupt wake-up. More... | |
#define | SYS_CTRL_I_MAP 0x400D2098 |
Interrupt map select. | |
#define | SYS_CTRL_RCGCRFC 0x400D20A8 |
RF Core clocks - active mode. | |
#define | SYS_CTRL_SCGCRFC 0x400D20AC |
RF Core clocks - Sleep mode. | |
#define | SYS_CTRL_DCGCRFC 0x400D20B0 |
RF Core clocks - PM0. | |
#define | SYS_CTRL_EMUOVR 0x400D20B4 |
Emulator override. | |
SYS_CTRL_RCGCGPT register bit masks | |
#define | SYS_CTRL_RCGCGPT_GPT3 0x00000008 |
GPT3 clock enable, CPU running. | |
#define | SYS_CTRL_RCGCGPT_GPT2 0x00000004 |
GPT2 clock enable, CPU running. | |
#define | SYS_CTRL_RCGCGPT_GPT1 0x00000002 |
GPT1 clock enable, CPU running. | |
#define | SYS_CTRL_RCGCGPT_GPT0 0x00000001 |
GPT0 clock enable, CPU running. | |
SYS_CTRL_SCGCGPT register bit masks | |
#define | SYS_CTRL_SCGCGPT_GPT3 0x00000008 |
GPT3 clock enable, CPU IDLE. | |
#define | SYS_CTRL_SCGCGPT_GPT2 0x00000004 |
GPT2 clock enable, CPU IDLE. | |
#define | SYS_CTRL_SCGCGPT_GPT1 0x00000002 |
GPT1 clock enable, CPU IDLE. | |
#define | SYS_CTRL_SCGCGPT_GPT0 0x00000001 |
GPT0 clock enable, CPU IDLE. | |
SYS_CTRL_DCGCGPT register bit masks | |
#define | SYS_CTRL_DCGCGPT_GPT3 0x00000008 |
GPT3 clock enable, PM0. | |
#define | SYS_CTRL_DCGCGPT_GPT2 0x00000004 |
GPT2 clock enable, PM0. | |
#define | SYS_CTRL_DCGCGPT_GPT1 0x00000002 |
GPT1 clock enable, PM0. | |
#define | SYS_CTRL_DCGCGPT_GPT0 0x00000001 |
GPT0 clock enable, PM0. | |
SYS_CTRL_SRGPT register bits | |
#define | SYS_CTRL_SRGPT_GPT3 0x00000008 |
GPT3 is reset. | |
#define | SYS_CTRL_SRGPT_GPT2 0x00000004 |
GPT2 is reset. | |
#define | SYS_CTRL_SRGPT_GPT1 0x00000002 |
GPT1 is reset. | |
#define | SYS_CTRL_SRGPT_GPT0 0x00000001 |
GPT0 is reset. | |
SYS_CTRL_RCGCSEC register bit masks | |
#define | SYS_CTRL_RCGCSEC_AES 0x00000002 |
AES clock enable, CPU running. | |
#define | SYS_CTRL_RCGCSEC_PKA 0x00000001 |
PKA clock enable, CPU running. | |
SYS_CTRL_SCGCSEC register bit masks | |
#define | SYS_CTRL_SCGCSEC_AES 0x00000002 |
AES clock enable, CPU IDLE. | |
#define | SYS_CTRL_SCGCSEC_PKA 0x00000001 |
PKA clock enable, CPU IDLE. | |
SYS_CTRL_DCGCSEC register bit masks | |
#define | SYS_CTRL_DCGCSEC_AES 0x00000002 |
AES clock enable, PM0. | |
#define | SYS_CTRL_DCGCSEC_PKA 0x00000001 |
PKA clock enable, PM0. | |
SYS_CTRL_SRSEC register bits | |
#define | SYS_CTRL_SRSEC_AES 0x00000002 |
AES is reset. | |
#define | SYS_CTRL_SRSEC_PKA 0x00000001 |
PKA is reset. | |
SYS_CTRL_PWRDBG register bits | |
#define | SYS_CTRL_PWRDBG_FORCE_WARM_RESET 0x00000008 |
SYS_CTRL_RCGCUART Register Bit-Masks | |
#define | SYS_CTRL_RCGCUART_UART1 0x00000002 |
UART1 Clock, CPU running. | |
#define | SYS_CTRL_RCGCUART_UART0 0x00000001 |
UART0 Clock, CPU running. | |
#define | SYS_CTRL_DCGCUART_UART1 0x00000002 |
UART1 Clock, PM0. | |
#define | SYS_CTRL_DCGCUART_UART0 0x00000001 |
UART0 Clock, PM0. | |
SYS_CTRL_SCGCUART Register Bit-Masks | |
#define | SYS_CTRL_SCGCUART_UART1 0x00000002 |
UART1 Clock, CPU IDLE. | |
#define | SYS_CTRL_SCGCUART_UART0 0x00000001 |
UART0 Clock, CPU IDLE. | |
SYS_CTRL_SRUART register bits | |
#define | SYS_CTRL_SRUART_UART1 0x00000002 |
UART1 module is reset. | |
#define | SYS_CTRL_SRUART_UART0 0x00000001 |
UART0 module is reset. | |
SYS_CTRL_PMCTL register values | |
#define | SYS_CTRL_PMCTL_PM3 0x00000003 |
PM3. | |
#define | SYS_CTRL_PMCTL_PM2 0x00000002 |
PM2. | |
#define | SYS_CTRL_PMCTL_PM1 0x00000001 |
PM1. | |
#define | SYS_CTRL_PMCTL_PM0 0x00000000 |
PM0. | |
SysCtrl 32-kHz oscillator selection | |
Prefer the crystal oscillator for time accuracy, and the RC oscillator for cost and power consumption | |
#define | SYS_CTRL_OSC32K_USE_XTAL 0 |
SysCtrl functions | |
int | sys_ctrl_get_reset_cause (void) |
Gets the cause of the last reset. More... | |
const char * | sys_ctrl_get_reset_cause_str (void) |
Gets a string describing the cause of the last reset. More... | |
void | sys_ctrl_init () |
Initialises the System Control Driver. More... | |
void | sys_ctrl_reset () |
Generates a warm reset through the SYS_CTRL_PWRDBG register. | |
uint32_t | sys_ctrl_get_sys_clock () |
Returns the actual system clock in Hz. | |
uint32_t | sys_ctrl_get_io_clock () |
Returns the actual io clock in Hz. | |
Driver for the cc2538 System Control Module.
#define SYS_CTRL_IWE 0x400D2094 |
interrupt wake-up.
Definition at line 91 of file sys-ctrl.h.
int sys_ctrl_get_reset_cause | ( | void | ) |
Gets the cause of the last reset.
SYS_CTRL_CLOCK_STA_RST_x
reset cause Definition at line 54 of file sys-ctrl.c.
Referenced by sys_ctrl_get_reset_cause_str().
const char * sys_ctrl_get_reset_cause_str | ( | void | ) |
Gets a string describing the cause of the last reset.
Definition at line 61 of file sys-ctrl.c.
References sys_ctrl_get_reset_cause().
void sys_ctrl_init | ( | ) |
Initialises the System Control Driver.
The main purpose of this function is to power up and select clocks and oscillators
Definition at line 74 of file sys-ctrl.c.
Referenced by soc_init().