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core_cm3.h
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1 /**************************************************************************//**
2  * @file core_cm3.h
3  * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
4  * @version V4.30
5  * @date 20. October 2015
6  ******************************************************************************/
7 /* Copyright (c) 2009 - 2015 ARM LIMITED
8 
9  All rights reserved.
10  Redistribution and use in source and binary forms, with or without
11  modification, are permitted provided that the following conditions are met:
12  - Redistributions of source code must retain the above copyright
13  notice, this list of conditions and the following disclaimer.
14  - Redistributions in binary form must reproduce the above copyright
15  notice, this list of conditions and the following disclaimer in the
16  documentation and/or other materials provided with the distribution.
17  - Neither the name of ARM nor the names of its contributors may be used
18  to endorse or promote products derived from this software without
19  specific prior written permission.
20  *
21  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
25  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31  POSSIBILITY OF SUCH DAMAGE.
32  ---------------------------------------------------------------------------*/
33 
34 
35 #if defined ( __ICCARM__ )
36  #pragma system_include /* treat file as system include file for MISRA check */
37 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
38  #pragma clang system_header /* treat file as system include file */
39 #endif
40 
41 #ifndef __CORE_CM3_H_GENERIC
42 #define __CORE_CM3_H_GENERIC
43 
44 #include <stdint.h>
45 
46 #ifdef __cplusplus
47  extern "C" {
48 #endif
49 
50 /**
51  CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
52  CMSIS violates the following MISRA-C:2004 rules:
53 
54  \li Required Rule 8.5, object/function definition in header file.<br>
55  Function definitions in header files are used to allow 'inlining'.
56 
57  \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
58  Unions are used for effective representation of core registers.
59 
60  \li Advisory Rule 19.7, Function-like macro defined.<br>
61  Function-like macros are used to allow more efficient code.
62  */
63 
64 
65 /*******************************************************************************
66  * CMSIS definitions
67  ******************************************************************************/
68 /**
69  \ingroup Cortex_M3
70  @{
71  */
72 
73 /* CMSIS CM3 definitions */
74 #define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
75 #define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
76 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
77  __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
78 
79 #define __CORTEX_M (0x03U) /*!< Cortex-M Core */
80 
81 
82 #if defined ( __CC_ARM )
83  #define __ASM __asm /*!< asm keyword for ARM Compiler */
84  #define __INLINE __inline /*!< inline keyword for ARM Compiler */
85  #define __STATIC_INLINE static __inline
86 
87 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
88  #define __ASM __asm /*!< asm keyword for ARM Compiler */
89  #define __INLINE __inline /*!< inline keyword for ARM Compiler */
90  #define __STATIC_INLINE static __inline
91 
92 #elif defined ( __GNUC__ )
93  #define __ASM __asm /*!< asm keyword for GNU Compiler */
94  #define __INLINE inline /*!< inline keyword for GNU Compiler */
95  #define __STATIC_INLINE static inline
96 
97 #elif defined ( __ICCARM__ )
98  #define __ASM __asm /*!< asm keyword for IAR Compiler */
99  #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
100  #define __STATIC_INLINE static inline
101 
102 #elif defined ( __TMS470__ )
103  #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
104  #define __STATIC_INLINE static inline
105 
106 #elif defined ( __TASKING__ )
107  #define __ASM __asm /*!< asm keyword for TASKING Compiler */
108  #define __INLINE inline /*!< inline keyword for TASKING Compiler */
109  #define __STATIC_INLINE static inline
110 
111 #elif defined ( __CSMC__ )
112  #define __packed
113  #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
114  #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
115  #define __STATIC_INLINE static inline
116 
117 #else
118  #error Unknown compiler
119 #endif
120 
121 /** __FPU_USED indicates whether an FPU is used or not.
122  This core does not support an FPU at all
123 */
124 #define __FPU_USED 0U
125 
126 #if defined ( __CC_ARM )
127  #if defined __TARGET_FPU_VFP
128  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
129  #endif
130 
131 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
132  #if defined __ARM_PCS_VFP
133  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
134  #endif
135 
136 #elif defined ( __GNUC__ )
137  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
138  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
139  #endif
140 
141 #elif defined ( __ICCARM__ )
142  #if defined __ARMVFP__
143  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
144  #endif
145 
146 #elif defined ( __TMS470__ )
147  #if defined __TI_VFP_SUPPORT__
148  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
149  #endif
150 
151 #elif defined ( __TASKING__ )
152  #if defined __FPU_VFP__
153  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
154  #endif
155 
156 #elif defined ( __CSMC__ )
157  #if ( __CSMC__ & 0x400U)
158  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
159  #endif
160 
161 #endif
162 
163 #include "core_cmInstr.h" /* Core Instruction Access */
164 #include "core_cmFunc.h" /* Core Function Access */
165 
166 #ifdef __cplusplus
167 }
168 #endif
169 
170 #endif /* __CORE_CM3_H_GENERIC */
171 
172 #ifndef __CMSIS_GENERIC
173 
174 #ifndef __CORE_CM3_H_DEPENDANT
175 #define __CORE_CM3_H_DEPENDANT
176 
177 #ifdef __cplusplus
178  extern "C" {
179 #endif
180 
181 /* check device defines and use defaults */
182 #if defined __CHECK_DEVICE_DEFINES
183  #ifndef __CM3_REV
184  #define __CM3_REV 0x0200U
185  #warning "__CM3_REV not defined in device header file; using default!"
186  #endif
187 
188  #ifndef __MPU_PRESENT
189  #define __MPU_PRESENT 0U
190  #warning "__MPU_PRESENT not defined in device header file; using default!"
191  #endif
192 
193  #ifndef __NVIC_PRIO_BITS
194  #define __NVIC_PRIO_BITS 4U
195  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
196  #endif
197 
198  #ifndef __Vendor_SysTickConfig
199  #define __Vendor_SysTickConfig 0U
200  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
201  #endif
202 #endif
203 
204 /* IO definitions (access restrictions to peripheral registers) */
205 /**
206  \defgroup CMSIS_glob_defs CMSIS Global Defines
207 
208  <strong>IO Type Qualifiers</strong> are used
209  \li to specify the access to peripheral variables.
210  \li for automatic generation of peripheral register debug information.
211 */
212 #ifdef __cplusplus
213  #define __I volatile /*!< Defines 'read only' permissions */
214 #else
215  #define __I volatile const /*!< Defines 'read only' permissions */
216 #endif
217 #define __O volatile /*!< Defines 'write only' permissions */
218 #define __IO volatile /*!< Defines 'read / write' permissions */
219 
220 /* following defines should be used for structure members */
221 #define __IM volatile const /*! Defines 'read only' structure member permissions */
222 #define __OM volatile /*! Defines 'write only' structure member permissions */
223 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
224 
225 /*@} end of group Cortex_M3 */
226 
227 
228 
229 /*******************************************************************************
230  * Register Abstraction
231  Core Register contain:
232  - Core Register
233  - Core NVIC Register
234  - Core SCB Register
235  - Core SysTick Register
236  - Core Debug Register
237  - Core MPU Register
238  ******************************************************************************/
239 /**
240  \defgroup CMSIS_core_register Defines and Type Definitions
241  \brief Type definitions and defines for Cortex-M processor based devices.
242 */
243 
244 /**
245  \ingroup CMSIS_core_register
246  \defgroup CMSIS_CORE Status and Control Registers
247  \brief Core Register type definitions.
248  @{
249  */
250 
251 /**
252  \brief Union type to access the Application Program Status Register (APSR).
253  */
254 typedef union
255 {
256  struct
257  {
258  uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
259  uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
260  uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
261  uint32_t C:1; /*!< bit: 29 Carry condition code flag */
262  uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
263  uint32_t N:1; /*!< bit: 31 Negative condition code flag */
264  } b; /*!< Structure used for bit access */
265  uint32_t w; /*!< Type used for word access */
266 } APSR_Type;
267 
268 /* APSR Register Definitions */
269 #define APSR_N_Pos 31U /*!< APSR: N Position */
270 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
271 
272 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
273 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
274 
275 #define APSR_C_Pos 29U /*!< APSR: C Position */
276 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
277 
278 #define APSR_V_Pos 28U /*!< APSR: V Position */
279 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
280 
281 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
282 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
283 
284 
285 /**
286  \brief Union type to access the Interrupt Program Status Register (IPSR).
287  */
288 typedef union
289 {
290  struct
291  {
292  uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
293  uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
294  } b; /*!< Structure used for bit access */
295  uint32_t w; /*!< Type used for word access */
296 } IPSR_Type;
297 
298 /* IPSR Register Definitions */
299 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
300 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
301 
302 
303 /**
304  \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
305  */
306 typedef union
307 {
308  struct
309  {
310  uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
311  uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
312  uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
313  uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
314  uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
315  uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
316  uint32_t C:1; /*!< bit: 29 Carry condition code flag */
317  uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
318  uint32_t N:1; /*!< bit: 31 Negative condition code flag */
319  } b; /*!< Structure used for bit access */
320  uint32_t w; /*!< Type used for word access */
321 } xPSR_Type;
322 
323 /* xPSR Register Definitions */
324 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
325 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
326 
327 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
328 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
329 
330 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
331 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
332 
333 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
334 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
335 
336 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
337 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
338 
339 #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
340 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
341 
342 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
343 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
344 
345 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
346 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
347 
348 
349 /**
350  \brief Union type to access the Control Registers (CONTROL).
351  */
352 typedef union
353 {
354  struct
355  {
356  uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
357  uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
358  uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
359  } b; /*!< Structure used for bit access */
360  uint32_t w; /*!< Type used for word access */
361 } CONTROL_Type;
362 
363 /* CONTROL Register Definitions */
364 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
365 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
366 
367 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
368 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
369 
370 /*@} end of group CMSIS_CORE */
371 
372 
373 /**
374  \ingroup CMSIS_core_register
375  \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
376  \brief Type definitions for the NVIC Registers
377  @{
378  */
379 
380 /**
381  \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
382  */
383 typedef struct
384 {
385  __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
386  uint32_t RESERVED0[24U];
387  __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
388  uint32_t RSERVED1[24U];
389  __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
390  uint32_t RESERVED2[24U];
391  __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
392  uint32_t RESERVED3[24U];
393  __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
394  uint32_t RESERVED4[56U];
395  __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
396  uint32_t RESERVED5[644U];
397  __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
398 } NVIC_Type;
399 
400 /* Software Triggered Interrupt Register Definitions */
401 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
402 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
403 
404 /*@} end of group CMSIS_NVIC */
405 
406 
407 /**
408  \ingroup CMSIS_core_register
409  \defgroup CMSIS_SCB System Control Block (SCB)
410  \brief Type definitions for the System Control Block Registers
411  @{
412  */
413 
414 /**
415  \brief Structure type to access the System Control Block (SCB).
416  */
417 typedef struct
418 {
419  __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
420  __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
421  __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
422  __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
423  __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
424  __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
425  __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
426  __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
427  __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
428  __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
429  __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
430  __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
431  __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
432  __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
433  __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
434  __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
435  __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
436  __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
437  __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
438  uint32_t RESERVED0[5U];
439  __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
440 } SCB_Type;
441 
442 /* SCB CPUID Register Definitions */
443 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
444 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
445 
446 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
447 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
448 
449 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
450 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
451 
452 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
453 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
454 
455 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
456 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
457 
458 /* SCB Interrupt Control State Register Definitions */
459 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
460 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
461 
462 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
463 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
464 
465 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
466 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
467 
468 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
469 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
470 
471 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
472 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
473 
474 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
475 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
476 
477 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
478 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
479 
480 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
481 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
482 
483 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
484 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
485 
486 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
487 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
488 
489 /* SCB Vector Table Offset Register Definitions */
490 #if (__CM3_REV < 0x0201U) /* core r2p1 */
491 #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
492 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
493 
494 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
495 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
496 #else
497 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
498 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
499 #endif
500 
501 /* SCB Application Interrupt and Reset Control Register Definitions */
502 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
503 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
504 
505 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
506 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
507 
508 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
509 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
510 
511 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
512 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
513 
514 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
515 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
516 
517 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
518 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
519 
520 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
521 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
522 
523 /* SCB System Control Register Definitions */
524 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
525 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
526 
527 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
528 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
529 
530 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
531 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
532 
533 /* SCB Configuration Control Register Definitions */
534 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
535 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
536 
537 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
538 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
539 
540 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
541 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
542 
543 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
544 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
545 
546 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
547 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
548 
549 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
550 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
551 
552 /* SCB System Handler Control and State Register Definitions */
553 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
554 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
555 
556 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
557 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
558 
559 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
560 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
561 
562 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
563 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
564 
565 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
566 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
567 
568 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
569 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
570 
571 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
572 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
573 
574 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
575 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
576 
577 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
578 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
579 
580 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
581 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
582 
583 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
584 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
585 
586 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
587 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
588 
589 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
590 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
591 
592 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
593 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
594 
595 /* SCB Configurable Fault Status Register Definitions */
596 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
597 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
598 
599 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
600 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
601 
602 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
603 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
604 
605 /* SCB Hard Fault Status Register Definitions */
606 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
607 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
608 
609 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
610 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
611 
612 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
613 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
614 
615 /* SCB Debug Fault Status Register Definitions */
616 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
617 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
618 
619 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
620 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
621 
622 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
623 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
624 
625 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
626 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
627 
628 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
629 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
630 
631 /*@} end of group CMSIS_SCB */
632 
633 
634 /**
635  \ingroup CMSIS_core_register
636  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
637  \brief Type definitions for the System Control and ID Register not in the SCB
638  @{
639  */
640 
641 /**
642  \brief Structure type to access the System Control and ID Register not in the SCB.
643  */
644 typedef struct
645 {
646  uint32_t RESERVED0[1U];
647  __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
648 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200U))
649  __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
650 #else
651  uint32_t RESERVED1[1U];
652 #endif
653 } SCnSCB_Type;
654 
655 /* Interrupt Controller Type Register Definitions */
656 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
657 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
658 
659 /* Auxiliary Control Register Definitions */
660 
661 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
662 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
663 
664 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
665 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
666 
667 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
668 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
669 
670 /*@} end of group CMSIS_SCnotSCB */
671 
672 
673 /**
674  \ingroup CMSIS_core_register
675  \defgroup CMSIS_SysTick System Tick Timer (SysTick)
676  \brief Type definitions for the System Timer Registers.
677  @{
678  */
679 
680 /**
681  \brief Structure type to access the System Timer (SysTick).
682  */
683 typedef struct
684 {
685  __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
686  __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
687  __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
688  __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
689 } SysTick_Type;
690 
691 /* SysTick Control / Status Register Definitions */
692 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
693 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
694 
695 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
696 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
697 
698 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
699 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
700 
701 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
702 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
703 
704 /* SysTick Reload Register Definitions */
705 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
706 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
707 
708 /* SysTick Current Register Definitions */
709 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
710 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
711 
712 /* SysTick Calibration Register Definitions */
713 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
714 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
715 
716 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
717 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
718 
719 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
720 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
721 
722 /*@} end of group CMSIS_SysTick */
723 
724 
725 /**
726  \ingroup CMSIS_core_register
727  \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
728  \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
729  @{
730  */
731 
732 /**
733  \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
734  */
735 typedef struct
736 {
737  __OM union
738  {
739  __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
740  __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
741  __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
742  } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
743  uint32_t RESERVED0[864U];
744  __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
745  uint32_t RESERVED1[15U];
746  __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
747  uint32_t RESERVED2[15U];
748  __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
749  uint32_t RESERVED3[29U];
750  __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
751  __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
752  __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
753  uint32_t RESERVED4[43U];
754  __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
755  __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
756  uint32_t RESERVED5[6U];
757  __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
758  __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
759  __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
760  __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
761  __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
762  __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
763  __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
764  __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
765  __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
766  __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
767  __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
768  __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
769 } ITM_Type;
770 
771 /* ITM Trace Privilege Register Definitions */
772 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
773 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
774 
775 /* ITM Trace Control Register Definitions */
776 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
777 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
778 
779 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
780 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
781 
782 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
783 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
784 
785 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
786 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
787 
788 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
789 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
790 
791 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
792 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
793 
794 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
795 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
796 
797 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
798 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
799 
800 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
801 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
802 
803 /* ITM Integration Write Register Definitions */
804 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
805 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
806 
807 /* ITM Integration Read Register Definitions */
808 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
809 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
810 
811 /* ITM Integration Mode Control Register Definitions */
812 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
813 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
814 
815 /* ITM Lock Status Register Definitions */
816 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
817 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
818 
819 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
820 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
821 
822 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
823 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
824 
825 /*@}*/ /* end of group CMSIS_ITM */
826 
827 
828 /**
829  \ingroup CMSIS_core_register
830  \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
831  \brief Type definitions for the Data Watchpoint and Trace (DWT)
832  @{
833  */
834 
835 /**
836  \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
837  */
838 typedef struct
839 {
840  __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
841  __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
842  __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
843  __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
844  __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
845  __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
846  __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
847  __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
848  __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
849  __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
850  __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
851  uint32_t RESERVED0[1U];
852  __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
853  __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
854  __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
855  uint32_t RESERVED1[1U];
856  __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
857  __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
858  __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
859  uint32_t RESERVED2[1U];
860  __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
861  __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
862  __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
863 } DWT_Type;
864 
865 /* DWT Control Register Definitions */
866 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
867 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
868 
869 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
870 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
871 
872 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
873 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
874 
875 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
876 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
877 
878 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
879 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
880 
881 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
882 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
883 
884 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
885 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
886 
887 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
888 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
889 
890 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
891 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
892 
893 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
894 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
895 
896 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
897 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
898 
899 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
900 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
901 
902 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
903 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
904 
905 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
906 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
907 
908 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
909 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
910 
911 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
912 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
913 
914 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
915 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
916 
917 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
918 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
919 
920 /* DWT CPI Count Register Definitions */
921 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
922 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
923 
924 /* DWT Exception Overhead Count Register Definitions */
925 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
926 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
927 
928 /* DWT Sleep Count Register Definitions */
929 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
930 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
931 
932 /* DWT LSU Count Register Definitions */
933 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
934 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
935 
936 /* DWT Folded-instruction Count Register Definitions */
937 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
938 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
939 
940 /* DWT Comparator Mask Register Definitions */
941 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
942 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
943 
944 /* DWT Comparator Function Register Definitions */
945 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
946 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
947 
948 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
949 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
950 
951 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
952 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
953 
954 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
955 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
956 
957 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
958 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
959 
960 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
961 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
962 
963 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
964 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
965 
966 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
967 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
968 
969 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
970 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
971 
972 /*@}*/ /* end of group CMSIS_DWT */
973 
974 
975 /**
976  \ingroup CMSIS_core_register
977  \defgroup CMSIS_TPI Trace Port Interface (TPI)
978  \brief Type definitions for the Trace Port Interface (TPI)
979  @{
980  */
981 
982 /**
983  \brief Structure type to access the Trace Port Interface Register (TPI).
984  */
985 typedef struct
986 {
987  __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
988  __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
989  uint32_t RESERVED0[2U];
990  __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
991  uint32_t RESERVED1[55U];
992  __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
993  uint32_t RESERVED2[131U];
994  __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
995  __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
996  __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
997  uint32_t RESERVED3[759U];
998  __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
999  __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
1000  __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1001  uint32_t RESERVED4[1U];
1002  __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1003  __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1004  __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
1005  uint32_t RESERVED5[39U];
1006  __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
1007  __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
1008  uint32_t RESERVED7[8U];
1009  __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1010  __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
1011 } TPI_Type;
1012 
1013 /* TPI Asynchronous Clock Prescaler Register Definitions */
1014 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
1015 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
1016 
1017 /* TPI Selected Pin Protocol Register Definitions */
1018 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
1019 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
1020 
1021 /* TPI Formatter and Flush Status Register Definitions */
1022 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
1023 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
1024 
1025 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
1026 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
1027 
1028 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
1029 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
1030 
1031 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
1032 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
1033 
1034 /* TPI Formatter and Flush Control Register Definitions */
1035 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
1036 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
1037 
1038 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
1039 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
1040 
1041 /* TPI TRIGGER Register Definitions */
1042 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
1043 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
1044 
1045 /* TPI Integration ETM Data Register Definitions (FIFO0) */
1046 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
1047 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
1048 
1049 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
1050 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
1051 
1052 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
1053 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
1054 
1055 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
1056 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
1057 
1058 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
1059 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
1060 
1061 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
1062 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
1063 
1064 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
1065 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
1066 
1067 /* TPI ITATBCTR2 Register Definitions */
1068 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
1069 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
1070 
1071 /* TPI Integration ITM Data Register Definitions (FIFO1) */
1072 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
1073 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
1074 
1075 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
1076 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
1077 
1078 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
1079 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
1080 
1081 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
1082 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
1083 
1084 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
1085 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
1086 
1087 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
1088 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
1089 
1090 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
1091 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
1092 
1093 /* TPI ITATBCTR0 Register Definitions */
1094 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
1095 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
1096 
1097 /* TPI Integration Mode Control Register Definitions */
1098 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
1099 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
1100 
1101 /* TPI DEVID Register Definitions */
1102 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
1103 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
1104 
1105 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
1106 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
1107 
1108 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
1109 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
1110 
1111 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
1112 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
1113 
1114 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
1115 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
1116 
1117 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
1118 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
1119 
1120 /* TPI DEVTYPE Register Definitions */
1121 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
1122 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
1123 
1124 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
1125 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
1126 
1127 /*@}*/ /* end of group CMSIS_TPI */
1128 
1129 
1130 #if (__MPU_PRESENT == 1U)
1131 /**
1132  \ingroup CMSIS_core_register
1133  \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1134  \brief Type definitions for the Memory Protection Unit (MPU)
1135  @{
1136  */
1137 
1138 /**
1139  \brief Structure type to access the Memory Protection Unit (MPU).
1140  */
1141 typedef struct
1142 {
1143  __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1144  __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1145  __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
1146  __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1147  __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
1148  __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
1149  __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
1150  __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
1151  __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
1152  __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
1153  __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
1154 } MPU_Type;
1155 
1156 /* MPU Type Register Definitions */
1157 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
1158 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1159 
1160 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
1161 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1162 
1163 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
1164 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
1165 
1166 /* MPU Control Register Definitions */
1167 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
1168 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1169 
1170 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
1171 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1172 
1173 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
1174 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
1175 
1176 /* MPU Region Number Register Definitions */
1177 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
1178 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
1179 
1180 /* MPU Region Base Address Register Definitions */
1181 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
1182 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
1183 
1184 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
1185 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
1186 
1187 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
1188 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
1189 
1190 /* MPU Region Attribute and Size Register Definitions */
1191 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
1192 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
1193 
1194 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
1195 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
1196 
1197 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
1198 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
1199 
1200 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
1201 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
1202 
1203 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
1204 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
1205 
1206 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
1207 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
1208 
1209 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
1210 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
1211 
1212 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
1213 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
1214 
1215 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
1216 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
1217 
1218 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
1219 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
1220 
1221 /*@} end of group CMSIS_MPU */
1222 #endif
1223 
1224 
1225 /**
1226  \ingroup CMSIS_core_register
1227  \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1228  \brief Type definitions for the Core Debug Registers
1229  @{
1230  */
1231 
1232 /**
1233  \brief Structure type to access the Core Debug Register (CoreDebug).
1234  */
1235 typedef struct
1236 {
1237  __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1238  __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1239  __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1240  __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1241 } CoreDebug_Type;
1242 
1243 /* Debug Halting Control and Status Register Definitions */
1244 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
1245 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1246 
1247 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
1248 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1249 
1250 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1251 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1252 
1253 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
1254 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1255 
1256 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
1257 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1258 
1259 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
1260 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1261 
1262 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
1263 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1264 
1265 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1266 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1267 
1268 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
1269 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1270 
1271 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
1272 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1273 
1274 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
1275 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1276 
1277 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1278 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1279 
1280 /* Debug Core Register Selector Register Definitions */
1281 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
1282 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1283 
1284 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
1285 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
1286 
1287 /* Debug Exception and Monitor Control Register Definitions */
1288 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
1289 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
1290 
1291 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
1292 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
1293 
1294 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
1295 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
1296 
1297 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
1298 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
1299 
1300 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
1301 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
1302 
1303 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
1304 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1305 
1306 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
1307 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
1308 
1309 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
1310 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1311 
1312 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
1313 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
1314 
1315 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
1316 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1317 
1318 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1319 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1320 
1321 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
1322 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
1323 
1324 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
1325 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1326 
1327 /*@} end of group CMSIS_CoreDebug */
1328 
1329 
1330 /**
1331  \ingroup CMSIS_core_register
1332  \defgroup CMSIS_core_bitfield Core register bit field macros
1333  \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
1334  @{
1335  */
1336 
1337 /**
1338  \brief Mask and shift a bit field value for use in a register bit range.
1339  \param[in] field Name of the register bit field.
1340  \param[in] value Value of the bit field.
1341  \return Masked and shifted value.
1342 */
1343 #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
1344 
1345 /**
1346  \brief Mask and shift a register value to extract a bit filed value.
1347  \param[in] field Name of the register bit field.
1348  \param[in] value Value of register.
1349  \return Masked and shifted bit field value.
1350 */
1351 #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
1352 
1353 /*@} end of group CMSIS_core_bitfield */
1354 
1355 
1356 /**
1357  \ingroup CMSIS_core_register
1358  \defgroup CMSIS_core_base Core Definitions
1359  \brief Definitions for base addresses, unions, and structures.
1360  @{
1361  */
1362 
1363 /* Memory mapping of Cortex-M3 Hardware */
1364 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1365 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1366 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1367 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1368 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1369 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1370 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1371 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1372 
1373 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
1374 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1375 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1376 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1377 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1378 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1379 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1380 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
1381 
1382 #if (__MPU_PRESENT == 1U)
1383  #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1384  #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1385 #endif
1386 
1387 /*@} */
1388 
1389 
1390 
1391 /*******************************************************************************
1392  * Hardware Abstraction Layer
1393  Core Function Interface contains:
1394  - Core NVIC Functions
1395  - Core SysTick Functions
1396  - Core Debug Functions
1397  - Core Register Access Functions
1398  ******************************************************************************/
1399 /**
1400  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1401 */
1402 
1403 
1404 
1405 /* ########################## NVIC functions #################################### */
1406 /**
1407  \ingroup CMSIS_Core_FunctionInterface
1408  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1409  \brief Functions that manage interrupts and exceptions via the NVIC.
1410  @{
1411  */
1412 
1413 /**
1414  \brief Set Priority Grouping
1415  \details Sets the priority grouping field using the required unlock sequence.
1416  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1417  Only values from 0..7 are used.
1418  In case of a conflict between priority grouping and available
1419  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1420  \param [in] PriorityGroup Priority grouping field.
1421  */
1422 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1423 {
1424  uint32_t reg_value;
1425  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1426 
1427  reg_value = SCB->AIRCR; /* read old register configuration */
1428  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
1429  reg_value = (reg_value |
1430  ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1431  (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
1432  SCB->AIRCR = reg_value;
1433 }
1434 
1435 
1436 /**
1437  \brief Get Priority Grouping
1438  \details Reads the priority grouping field from the NVIC Interrupt Controller.
1439  \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1440  */
1441 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
1442 {
1443  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1444 }
1445 
1446 
1447 /**
1448  \brief Get External Interrupt Enable State
1449  \details Returns whether a device-specific interrupt is enabled in the NVIC interrupt controller.
1450  \param [in] IRQn External interrupt number. Value cannot be negative.
1451  \return 0 Interrupt is disabled.
1452  \return 1 Interrupt is enabled.
1453  */
1454 __STATIC_INLINE uint32_t NVIC_IsIRQEnabled(IRQn_Type IRQn)
1455 {
1456  return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1457 }
1458 
1459 
1460 /**
1461  \brief Enable External Interrupt
1462  \details Enables a device-specific interrupt in the NVIC interrupt controller.
1463  \param [in] IRQn External interrupt number. Value cannot be negative.
1464  */
1465 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1466 {
1467  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1468 }
1469 
1470 
1471 /**
1472  \brief Disable External Interrupt
1473  \details Disables a device-specific interrupt in the NVIC interrupt controller.
1474  \param [in] IRQn External interrupt number. Value cannot be negative.
1475  */
1476 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1477 {
1478  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1479 }
1480 
1481 
1482 /**
1483  \brief Get Pending Interrupt
1484  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
1485  \param [in] IRQn Interrupt number.
1486  \return 0 Interrupt status is not pending.
1487  \return 1 Interrupt status is pending.
1488  */
1489 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
1490 {
1491  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1492 }
1493 
1494 
1495 /**
1496  \brief Set Pending Interrupt
1497  \details Sets the pending bit of an external interrupt.
1498  \param [in] IRQn Interrupt number. Value cannot be negative.
1499  */
1500 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1501 {
1502  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1503 }
1504 
1505 
1506 /**
1507  \brief Clear Pending Interrupt
1508  \details Clears the pending bit of an external interrupt.
1509  \param [in] IRQn External interrupt number. Value cannot be negative.
1510  */
1511 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1512 {
1513  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1514 }
1515 
1516 
1517 /**
1518  \brief Get Active Interrupt
1519  \details Reads the active register in NVIC and returns the active bit.
1520  \param [in] IRQn Interrupt number.
1521  \return 0 Interrupt status is not active.
1522  \return 1 Interrupt status is active.
1523  */
1524 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
1525 {
1526  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1527 }
1528 
1529 
1530 /**
1531  \brief Set Interrupt Priority
1532  \details Sets the priority of an interrupt.
1533  \note The priority cannot be set for every core interrupt.
1534  \param [in] IRQn Interrupt number.
1535  \param [in] priority Priority to set.
1536  */
1537 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1538 {
1539  if ((int32_t)(IRQn) < 0)
1540  {
1541  SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1542  }
1543  else
1544  {
1545  NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1546  }
1547 }
1548 
1549 
1550 /**
1551  \brief Get Interrupt Priority
1552  \details Reads the priority of an interrupt.
1553  The interrupt number can be positive to specify an external (device specific) interrupt,
1554  or negative to specify an internal (core) interrupt.
1555  \param [in] IRQn Interrupt number.
1556  \return Interrupt Priority.
1557  Value is aligned automatically to the implemented priority bits of the microcontroller.
1558  */
1559 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1560 {
1561 
1562  if ((int32_t)(IRQn) < 0)
1563  {
1564  return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
1565  }
1566  else
1567  {
1568  return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
1569  }
1570 }
1571 
1572 
1573 /**
1574  \brief Encode Priority
1575  \details Encodes the priority for an interrupt with the given priority group,
1576  preemptive priority value, and subpriority value.
1577  In case of a conflict between priority grouping and available
1578  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1579  \param [in] PriorityGroup Used priority group.
1580  \param [in] PreemptPriority Preemptive priority value (starting from 0).
1581  \param [in] SubPriority Subpriority value (starting from 0).
1582  \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
1583  */
1584 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1585 {
1586  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1587  uint32_t PreemptPriorityBits;
1588  uint32_t SubPriorityBits;
1589 
1590  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1591  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1592 
1593  return (
1594  ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1595  ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1596  );
1597 }
1598 
1599 
1600 /**
1601  \brief Decode Priority
1602  \details Decodes an interrupt priority value with a given priority group to
1603  preemptive priority value and subpriority value.
1604  In case of a conflict between priority grouping and available
1605  priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
1606  \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
1607  \param [in] PriorityGroup Used priority group.
1608  \param [out] pPreemptPriority Preemptive priority value (starting from 0).
1609  \param [out] pSubPriority Subpriority value (starting from 0).
1610  */
1611 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
1612 {
1613  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1614  uint32_t PreemptPriorityBits;
1615  uint32_t SubPriorityBits;
1616 
1617  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1618  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1619 
1620  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1621  *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1622 }
1623 
1624 
1625 /**
1626  \brief System Reset
1627  \details Initiates a system reset request to reset the MCU.
1628  */
1629 __STATIC_INLINE void NVIC_SystemReset(void)
1630 {
1631  __DSB(); /* Ensure all outstanding memory accesses included
1632  buffered write are completed before reset */
1633  SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1634  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1635  SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
1636  __DSB(); /* Ensure completion of memory access */
1637 
1638  for(;;) /* wait until reset */
1639  {
1640  __NOP();
1641  }
1642 }
1643 
1644 /*@} end of CMSIS_Core_NVICFunctions */
1645 
1646 
1647 
1648 /* ################################## SysTick function ############################################ */
1649 /**
1650  \ingroup CMSIS_Core_FunctionInterface
1651  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
1652  \brief Functions that configure the System.
1653  @{
1654  */
1655 
1656 #if (__Vendor_SysTickConfig == 0U)
1657 
1658 /**
1659  \brief System Tick Configuration
1660  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
1661  Counter is in free running mode to generate periodic interrupts.
1662  \param [in] ticks Number of ticks between two interrupts.
1663  \return 0 Function succeeded.
1664  \return 1 Function failed.
1665  \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1666  function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
1667  must contain a vendor-specific implementation of this function.
1668  */
1669 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1670 {
1671  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
1672  {
1673  return (1UL); /* Reload value impossible */
1674  }
1675 
1676  SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
1677  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
1678  SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
1681  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1682  return (0UL); /* Function successful */
1683 }
1684 
1685 #endif
1686 
1687 /*@} end of CMSIS_Core_SysTickFunctions */
1688 
1689 
1690 
1691 /* ##################################### Debug In/Output function ########################################### */
1692 /**
1693  \ingroup CMSIS_Core_FunctionInterface
1694  \defgroup CMSIS_core_DebugFunctions ITM Functions
1695  \brief Functions that access the ITM debug interface.
1696  @{
1697  */
1698 
1699 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
1700 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
1701 
1702 
1703 /**
1704  \brief ITM Send Character
1705  \details Transmits a character via the ITM channel 0, and
1706  \li Just returns when no debugger is connected that has booked the output.
1707  \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
1708  \param [in] ch Character to transmit.
1709  \returns Character to transmit.
1710  */
1711 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
1712 {
1713  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
1714  ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
1715  {
1716  while (ITM->PORT[0U].u32 == 0UL)
1717  {
1718  __NOP();
1719  }
1720  ITM->PORT[0U].u8 = (uint8_t)ch;
1721  }
1722  return (ch);
1723 }
1724 
1725 
1726 /**
1727  \brief ITM Receive Character
1728  \details Inputs a character via the external variable \ref ITM_RxBuffer.
1729  \return Received character.
1730  \return -1 No character pending.
1731  */
1732 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
1733 {
1734  int32_t ch = -1; /* no character available */
1735 
1736  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
1737  {
1738  ch = ITM_RxBuffer;
1739  ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
1740  }
1741 
1742  return (ch);
1743 }
1744 
1745 
1746 /**
1747  \brief ITM Check Character
1748  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
1749  \return 0 No character available.
1750  \return 1 Character available.
1751  */
1752 __STATIC_INLINE int32_t ITM_CheckChar (void)
1753 {
1754 
1755  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
1756  {
1757  return (0); /* no character available */
1758  }
1759  else
1760  {
1761  return (1); /* character available */
1762  }
1763 }
1764 
1765 /*@} end of CMSIS_core_DebugFunctions */
1766 
1767 
1768 
1769 
1770 #ifdef __cplusplus
1771 }
1772 #endif
1773 
1774 #endif /* __CORE_CM3_H_DEPENDANT */
1775 
1776 #endif /* __CMSIS_GENERIC */
uint32_t Q
Definition: core_cm3.h:314
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition: core_cm3.h:1611
CMSIS Cortex-M Core Function Access Header File.
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Definition: core_cm3.h:1752
IRQn
Definition: cc2538_cm3.h:64
15 System Tick Interrupt
Definition: cc2538_cm3.h:75
uint32_t IT
Definition: core_cm3.h:313
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_cm3.h:502
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_cm0.h:362
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_cm3.h:696
Structure type to access the System Control Block (SCB).
Definition: core_cm0.h:389
#define ITM
Definition: core_cm3.h:1377
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition: core_cm3.h:838
CMSIS Cortex-M Core Instruction Access Header File.
__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch)
ITM Send Character.
Definition: core_cm3.h:1711
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: core_cm3.h:1584
#define ITM_RXBUFFER_EMPTY
Definition: core_cm3.h:1700
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_cm0.h:701
volatile int32_t ITM_RxBuffer
#define SysTick_CTRL_TICKINT_Msk
Definition: core_cm3.h:699
#define SCB
Definition: core_cm3.h:1374
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Disable External Interrupt.
Definition: core_cm0.h:653
Structure type to access the System Timer (SysTick).
Definition: core_cm0.h:496
Structure type to access the Core Debug Register (CoreDebug).
Definition: core_cm3.h:1235
__STATIC_INLINE void NVIC_SystemReset(void)
System Reset.
Definition: core_cm0.h:743
Union type to access the Application Program Status Register (APSR).
Definition: core_cm0.h:247
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Enable External Interrupt.
Definition: core_cm0.h:642
#define SCB_AIRCR_VECTKEY_Msk
Definition: core_cm3.h:503
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_cm0.h:666
__STATIC_INLINE uint32_t NVIC_IsIRQEnabled(IRQn_Type IRQn)
Get External Interrupt Enable State.
Definition: core_cm0.h:631
#define SysTick
Definition: core_cm3.h:1375
__STATIC_INLINE void __NOP(void)
No Operation.
Definition: cmsis_gcc.h:373
#define SCB_AIRCR_PRIGROUP_Msk
Definition: core_cm3.h:512
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
System Tick Configuration.
Definition: core_cm0.h:782
Union type to access the Control Registers (CONTROL).
Definition: core_cm0.h:334
Structure type to access the Trace Port Interface Register (TPI).
Definition: core_cm3.h:985
#define NVIC
Definition: core_cm3.h:1376
#define SysTick_LOAD_RELOAD_Msk
Definition: core_cm3.h:706
Structure type to access the System Control and ID Register not in the SCB.
Definition: core_cm3.h:644
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_cm0.h:677
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_cm0.h:688
__STATIC_INLINE void __DSB(void)
Data Synchronization Barrier.
Definition: cmsis_gcc.h:427
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_cm0.h:277
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Definition: core_cm3.h:1732
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_cm0.h:295
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_cm0.h:725
#define SysTick_CTRL_ENABLE_Msk
Definition: core_cm3.h:702
uint32_t Q
Definition: core_cm3.h:259
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition: core_cm3.h:1524
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
Definition: core_cm3.h:1422
#define __NVIC_PRIO_BITS
Number of Bits used for Priority Levels.
Definition: cc2538_cm3.h:126
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
Definition: core_cm3.h:1441
#define ITM_TCR_ITMENA_Msk
Definition: core_cm3.h:801
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_cm3.h:515
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition: core_cm3.h:735
#define SCB_AIRCR_PRIGROUP_Pos
Definition: core_cm3.h:511