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core_cm0plus.h
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1 /**************************************************************************//**
2  * @file core_cm0plus.h
3  * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
4  * @version V4.30
5  * @date 20. October 2015
6  ******************************************************************************/
7 /* Copyright (c) 2009 - 2015 ARM LIMITED
8 
9  All rights reserved.
10  Redistribution and use in source and binary forms, with or without
11  modification, are permitted provided that the following conditions are met:
12  - Redistributions of source code must retain the above copyright
13  notice, this list of conditions and the following disclaimer.
14  - Redistributions in binary form must reproduce the above copyright
15  notice, this list of conditions and the following disclaimer in the
16  documentation and/or other materials provided with the distribution.
17  - Neither the name of ARM nor the names of its contributors may be used
18  to endorse or promote products derived from this software without
19  specific prior written permission.
20  *
21  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
25  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31  POSSIBILITY OF SUCH DAMAGE.
32  ---------------------------------------------------------------------------*/
33 
34 
35 #if defined ( __ICCARM__ )
36  #pragma system_include /* treat file as system include file for MISRA check */
37 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
38  #pragma clang system_header /* treat file as system include file */
39 #endif
40 
41 #ifndef __CORE_CM0PLUS_H_GENERIC
42 #define __CORE_CM0PLUS_H_GENERIC
43 
44 #include <stdint.h>
45 
46 #ifdef __cplusplus
47  extern "C" {
48 #endif
49 
50 /**
51  CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
52  CMSIS violates the following MISRA-C:2004 rules:
53 
54  \li Required Rule 8.5, object/function definition in header file.<br>
55  Function definitions in header files are used to allow 'inlining'.
56 
57  \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
58  Unions are used for effective representation of core registers.
59 
60  \li Advisory Rule 19.7, Function-like macro defined.<br>
61  Function-like macros are used to allow more efficient code.
62  */
63 
64 
65 /*******************************************************************************
66  * CMSIS definitions
67  ******************************************************************************/
68 /**
69  \ingroup Cortex_M0_plus
70  @{
71  */
72 
73 /* CMSIS CM0+ definitions */
74 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
75 #define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
76 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
77  __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
78 
79 #define __CORTEX_M (0x00U) /*!< Cortex-M Core */
80 
81 
82 #if defined ( __CC_ARM )
83  #define __ASM __asm /*!< asm keyword for ARM Compiler */
84  #define __INLINE __inline /*!< inline keyword for ARM Compiler */
85  #define __STATIC_INLINE static __inline
86 
87 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
88  #define __ASM __asm /*!< asm keyword for ARM Compiler */
89  #define __INLINE __inline /*!< inline keyword for ARM Compiler */
90  #define __STATIC_INLINE static __inline
91 
92 #elif defined ( __GNUC__ )
93  #define __ASM __asm /*!< asm keyword for GNU Compiler */
94  #define __INLINE inline /*!< inline keyword for GNU Compiler */
95  #define __STATIC_INLINE static inline
96 
97 #elif defined ( __ICCARM__ )
98  #define __ASM __asm /*!< asm keyword for IAR Compiler */
99  #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
100  #define __STATIC_INLINE static inline
101 
102 #elif defined ( __TMS470__ )
103  #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
104  #define __STATIC_INLINE static inline
105 
106 #elif defined ( __TASKING__ )
107  #define __ASM __asm /*!< asm keyword for TASKING Compiler */
108  #define __INLINE inline /*!< inline keyword for TASKING Compiler */
109  #define __STATIC_INLINE static inline
110 
111 #elif defined ( __CSMC__ )
112  #define __packed
113  #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
114  #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
115  #define __STATIC_INLINE static inline
116 
117 #else
118  #error Unknown compiler
119 #endif
120 
121 /** __FPU_USED indicates whether an FPU is used or not.
122  This core does not support an FPU at all
123 */
124 #define __FPU_USED 0U
125 
126 #if defined ( __CC_ARM )
127  #if defined __TARGET_FPU_VFP
128  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
129  #endif
130 
131 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
132  #if defined __ARM_PCS_VFP
133  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
134  #endif
135 
136 #elif defined ( __GNUC__ )
137  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
138  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
139  #endif
140 
141 #elif defined ( __ICCARM__ )
142  #if defined __ARMVFP__
143  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
144  #endif
145 
146 #elif defined ( __TMS470__ )
147  #if defined __TI_VFP_SUPPORT__
148  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
149  #endif
150 
151 #elif defined ( __TASKING__ )
152  #if defined __FPU_VFP__
153  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
154  #endif
155 
156 #elif defined ( __CSMC__ )
157  #if ( __CSMC__ & 0x400U)
158  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
159  #endif
160 
161 #endif
162 
163 #include "core_cmInstr.h" /* Core Instruction Access */
164 #include "core_cmFunc.h" /* Core Function Access */
165 
166 #ifdef __cplusplus
167 }
168 #endif
169 
170 #endif /* __CORE_CM0PLUS_H_GENERIC */
171 
172 #ifndef __CMSIS_GENERIC
173 
174 #ifndef __CORE_CM0PLUS_H_DEPENDANT
175 #define __CORE_CM0PLUS_H_DEPENDANT
176 
177 #ifdef __cplusplus
178  extern "C" {
179 #endif
180 
181 /* check device defines and use defaults */
182 #if defined __CHECK_DEVICE_DEFINES
183  #ifndef __CM0PLUS_REV
184  #define __CM0PLUS_REV 0x0000U
185  #warning "__CM0PLUS_REV not defined in device header file; using default!"
186  #endif
187 
188  #ifndef __MPU_PRESENT
189  #define __MPU_PRESENT 0U
190  #warning "__MPU_PRESENT not defined in device header file; using default!"
191  #endif
192 
193  #ifndef __VTOR_PRESENT
194  #define __VTOR_PRESENT 0U
195  #warning "__VTOR_PRESENT not defined in device header file; using default!"
196  #endif
197 
198  #ifndef __NVIC_PRIO_BITS
199  #define __NVIC_PRIO_BITS 2U
200  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
201  #endif
202 
203  #ifndef __Vendor_SysTickConfig
204  #define __Vendor_SysTickConfig 0U
205  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
206  #endif
207 #endif
208 
209 /* IO definitions (access restrictions to peripheral registers) */
210 /**
211  \defgroup CMSIS_glob_defs CMSIS Global Defines
212 
213  <strong>IO Type Qualifiers</strong> are used
214  \li to specify the access to peripheral variables.
215  \li for automatic generation of peripheral register debug information.
216 */
217 #ifdef __cplusplus
218  #define __I volatile /*!< Defines 'read only' permissions */
219 #else
220  #define __I volatile const /*!< Defines 'read only' permissions */
221 #endif
222 #define __O volatile /*!< Defines 'write only' permissions */
223 #define __IO volatile /*!< Defines 'read / write' permissions */
224 
225 /* following defines should be used for structure members */
226 #define __IM volatile const /*! Defines 'read only' structure member permissions */
227 #define __OM volatile /*! Defines 'write only' structure member permissions */
228 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
229 
230 /*@} end of group Cortex-M0+ */
231 
232 
233 
234 /*******************************************************************************
235  * Register Abstraction
236  Core Register contain:
237  - Core Register
238  - Core NVIC Register
239  - Core SCB Register
240  - Core SysTick Register
241  - Core MPU Register
242  ******************************************************************************/
243 /**
244  \defgroup CMSIS_core_register Defines and Type Definitions
245  \brief Type definitions and defines for Cortex-M processor based devices.
246 */
247 
248 /**
249  \ingroup CMSIS_core_register
250  \defgroup CMSIS_CORE Status and Control Registers
251  \brief Core Register type definitions.
252  @{
253  */
254 
255 /**
256  \brief Union type to access the Application Program Status Register (APSR).
257  */
258 typedef union
259 {
260  struct
261  {
262  uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
263  uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
264  uint32_t C:1; /*!< bit: 29 Carry condition code flag */
265  uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
266  uint32_t N:1; /*!< bit: 31 Negative condition code flag */
267  } b; /*!< Structure used for bit access */
268  uint32_t w; /*!< Type used for word access */
269 } APSR_Type;
270 
271 /* APSR Register Definitions */
272 #define APSR_N_Pos 31U /*!< APSR: N Position */
273 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
274 
275 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
276 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
277 
278 #define APSR_C_Pos 29U /*!< APSR: C Position */
279 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
280 
281 #define APSR_V_Pos 28U /*!< APSR: V Position */
282 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
283 
284 
285 /**
286  \brief Union type to access the Interrupt Program Status Register (IPSR).
287  */
288 typedef union
289 {
290  struct
291  {
292  uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
293  uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
294  } b; /*!< Structure used for bit access */
295  uint32_t w; /*!< Type used for word access */
296 } IPSR_Type;
297 
298 /* IPSR Register Definitions */
299 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
300 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
301 
302 
303 /**
304  \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
305  */
306 typedef union
307 {
308  struct
309  {
310  uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
311  uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
312  uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
313  uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
314  uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
315  uint32_t C:1; /*!< bit: 29 Carry condition code flag */
316  uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
317  uint32_t N:1; /*!< bit: 31 Negative condition code flag */
318  } b; /*!< Structure used for bit access */
319  uint32_t w; /*!< Type used for word access */
320 } xPSR_Type;
321 
322 /* xPSR Register Definitions */
323 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
324 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
325 
326 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
327 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
328 
329 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
330 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
331 
332 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
333 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
334 
335 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
336 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
337 
338 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
339 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
340 
341 
342 /**
343  \brief Union type to access the Control Registers (CONTROL).
344  */
345 typedef union
346 {
347  struct
348  {
349  uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
350  uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
351  uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
352  } b; /*!< Structure used for bit access */
353  uint32_t w; /*!< Type used for word access */
354 } CONTROL_Type;
355 
356 /* CONTROL Register Definitions */
357 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
358 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
359 
360 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
361 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
362 
363 /*@} end of group CMSIS_CORE */
364 
365 
366 /**
367  \ingroup CMSIS_core_register
368  \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
369  \brief Type definitions for the NVIC Registers
370  @{
371  */
372 
373 /**
374  \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
375  */
376 typedef struct
377 {
378  __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
379  uint32_t RESERVED0[31U];
380  __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
381  uint32_t RSERVED1[31U];
382  __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
383  uint32_t RESERVED2[31U];
384  __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
385  uint32_t RESERVED3[31U];
386  uint32_t RESERVED4[64U];
387  __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
388 } NVIC_Type;
389 
390 /*@} end of group CMSIS_NVIC */
391 
392 
393 /**
394  \ingroup CMSIS_core_register
395  \defgroup CMSIS_SCB System Control Block (SCB)
396  \brief Type definitions for the System Control Block Registers
397  @{
398  */
399 
400 /**
401  \brief Structure type to access the System Control Block (SCB).
402  */
403 typedef struct
404 {
405  __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
406  __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
407 #if (__VTOR_PRESENT == 1U)
408  __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
409 #else
410  uint32_t RESERVED0;
411 #endif
412  __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
413  __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
414  __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
415  uint32_t RESERVED1;
416  __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
417  __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
418 } SCB_Type;
419 
420 /* SCB CPUID Register Definitions */
421 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
422 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
423 
424 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
425 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
426 
427 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
428 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
429 
430 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
431 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
432 
433 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
434 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
435 
436 /* SCB Interrupt Control State Register Definitions */
437 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
438 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
439 
440 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
441 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
442 
443 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
444 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
445 
446 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
447 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
448 
449 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
450 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
451 
452 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
453 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
454 
455 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
456 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
457 
458 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
459 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
460 
461 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
462 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
463 
464 #if (__VTOR_PRESENT == 1U)
465 /* SCB Interrupt Control State Register Definitions */
466 #define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
467 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
468 #endif
469 
470 /* SCB Application Interrupt and Reset Control Register Definitions */
471 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
472 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
473 
474 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
475 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
476 
477 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
478 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
479 
480 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
481 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
482 
483 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
484 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
485 
486 /* SCB System Control Register Definitions */
487 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
488 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
489 
490 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
491 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
492 
493 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
494 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
495 
496 /* SCB Configuration Control Register Definitions */
497 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
498 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
499 
500 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
501 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
502 
503 /* SCB System Handler Control and State Register Definitions */
504 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
505 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
506 
507 /*@} end of group CMSIS_SCB */
508 
509 
510 /**
511  \ingroup CMSIS_core_register
512  \defgroup CMSIS_SysTick System Tick Timer (SysTick)
513  \brief Type definitions for the System Timer Registers.
514  @{
515  */
516 
517 /**
518  \brief Structure type to access the System Timer (SysTick).
519  */
520 typedef struct
521 {
522  __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
523  __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
524  __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
525  __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
526 } SysTick_Type;
527 
528 /* SysTick Control / Status Register Definitions */
529 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
530 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
531 
532 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
533 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
534 
535 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
536 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
537 
538 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
539 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
540 
541 /* SysTick Reload Register Definitions */
542 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
543 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
544 
545 /* SysTick Current Register Definitions */
546 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
547 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
548 
549 /* SysTick Calibration Register Definitions */
550 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
551 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
552 
553 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
554 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
555 
556 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
557 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
558 
559 /*@} end of group CMSIS_SysTick */
560 
561 #if (__MPU_PRESENT == 1U)
562 /**
563  \ingroup CMSIS_core_register
564  \defgroup CMSIS_MPU Memory Protection Unit (MPU)
565  \brief Type definitions for the Memory Protection Unit (MPU)
566  @{
567  */
568 
569 /**
570  \brief Structure type to access the Memory Protection Unit (MPU).
571  */
572 typedef struct
573 {
574  __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
575  __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
576  __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
577  __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
578  __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
579 } MPU_Type;
580 
581 /* MPU Type Register Definitions */
582 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
583 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
584 
585 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
586 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
587 
588 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
589 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
590 
591 /* MPU Control Register Definitions */
592 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
593 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
594 
595 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
596 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
597 
598 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
599 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
600 
601 /* MPU Region Number Register Definitions */
602 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
603 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
604 
605 /* MPU Region Base Address Register Definitions */
606 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
607 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
608 
609 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
610 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
611 
612 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
613 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
614 
615 /* MPU Region Attribute and Size Register Definitions */
616 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
617 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
618 
619 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
620 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
621 
622 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
623 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
624 
625 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
626 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
627 
628 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
629 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
630 
631 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
632 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
633 
634 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
635 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
636 
637 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
638 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
639 
640 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
641 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
642 
643 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
644 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
645 
646 /*@} end of group CMSIS_MPU */
647 #endif
648 
649 
650 /**
651  \ingroup CMSIS_core_register
652  \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
653  \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
654  Therefore they are not covered by the Cortex-M0+ header file.
655  @{
656  */
657 /*@} end of group CMSIS_CoreDebug */
658 
659 
660 /**
661  \ingroup CMSIS_core_register
662  \defgroup CMSIS_core_bitfield Core register bit field macros
663  \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
664  @{
665  */
666 
667 /**
668  \brief Mask and shift a bit field value for use in a register bit range.
669  \param[in] field Name of the register bit field.
670  \param[in] value Value of the bit field.
671  \return Masked and shifted value.
672 */
673 #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
674 
675 /**
676  \brief Mask and shift a register value to extract a bit filed value.
677  \param[in] field Name of the register bit field.
678  \param[in] value Value of register.
679  \return Masked and shifted bit field value.
680 */
681 #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
682 
683 /*@} end of group CMSIS_core_bitfield */
684 
685 
686 /**
687  \ingroup CMSIS_core_register
688  \defgroup CMSIS_core_base Core Definitions
689  \brief Definitions for base addresses, unions, and structures.
690  @{
691  */
692 
693 /* Memory mapping of Cortex-M0+ Hardware */
694 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
695 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
696 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
697 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
698 
699 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
700 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
701 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
702 
703 #if (__MPU_PRESENT == 1U)
704  #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
705  #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
706 #endif
707 
708 /*@} */
709 
710 
711 
712 /*******************************************************************************
713  * Hardware Abstraction Layer
714  Core Function Interface contains:
715  - Core NVIC Functions
716  - Core SysTick Functions
717  - Core Register Access Functions
718  ******************************************************************************/
719 /**
720  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
721 */
722 
723 
724 
725 /* ########################## NVIC functions #################################### */
726 /**
727  \ingroup CMSIS_Core_FunctionInterface
728  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
729  \brief Functions that manage interrupts and exceptions via the NVIC.
730  @{
731  */
732 
733 /* Interrupt Priorities are WORD accessible only under ARMv6M */
734 /* The following MACROS handle generation of the register offset and byte masks */
735 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
736 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
737 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
738 
739 
740 /**
741  \brief Get External Interrupt Enable State
742  \details Returns whether a device-specific interrupt is enabled in the NVIC interrupt controller.
743  \param [in] IRQn External interrupt number. Value cannot be negative.
744  \return 0 Interrupt is disabled.
745  \return 1 Interrupt is enabled.
746  */
747 __STATIC_INLINE uint32_t NVIC_IsIRQEnabled(IRQn_Type IRQn)
748 {
749  return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
750 }
751 
752 
753 /**
754  \brief Enable External Interrupt
755  \details Enables a device-specific interrupt in the NVIC interrupt controller.
756  \param [in] IRQn External interrupt number. Value cannot be negative.
757  */
758 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
759 {
760  NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
761 }
762 
763 
764 /**
765  \brief Disable External Interrupt
766  \details Disables a device-specific interrupt in the NVIC interrupt controller.
767  \param [in] IRQn External interrupt number. Value cannot be negative.
768  */
769 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
770 {
771  NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
772 }
773 
774 
775 /**
776  \brief Get Pending Interrupt
777  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
778  \param [in] IRQn Interrupt number.
779  \return 0 Interrupt status is not pending.
780  \return 1 Interrupt status is pending.
781  */
782 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
783 {
784  return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
785 }
786 
787 
788 /**
789  \brief Set Pending Interrupt
790  \details Sets the pending bit of an external interrupt.
791  \param [in] IRQn Interrupt number. Value cannot be negative.
792  */
793 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
794 {
795  NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
796 }
797 
798 
799 /**
800  \brief Clear Pending Interrupt
801  \details Clears the pending bit of an external interrupt.
802  \param [in] IRQn External interrupt number. Value cannot be negative.
803  */
804 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
805 {
806  NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
807 }
808 
809 
810 /**
811  \brief Set Interrupt Priority
812  \details Sets the priority of an interrupt.
813  \note The priority cannot be set for every core interrupt.
814  \param [in] IRQn Interrupt number.
815  \param [in] priority Priority to set.
816  */
817 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
818 {
819  if ((int32_t)(IRQn) < 0)
820  {
821  SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
822  (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
823  }
824  else
825  {
826  NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
827  (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
828  }
829 }
830 
831 
832 /**
833  \brief Get Interrupt Priority
834  \details Reads the priority of an interrupt.
835  The interrupt number can be positive to specify an external (device specific) interrupt,
836  or negative to specify an internal (core) interrupt.
837  \param [in] IRQn Interrupt number.
838  \return Interrupt Priority.
839  Value is aligned automatically to the implemented priority bits of the microcontroller.
840  */
841 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
842 {
843 
844  if ((int32_t)(IRQn) < 0)
845  {
846  return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
847  }
848  else
849  {
850  return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
851  }
852 }
853 
854 
855 /**
856  \brief System Reset
857  \details Initiates a system reset request to reset the MCU.
858  */
859 __STATIC_INLINE void NVIC_SystemReset(void)
860 {
861  __DSB(); /* Ensure all outstanding memory accesses included
862  buffered write are completed before reset */
863  SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
865  __DSB(); /* Ensure completion of memory access */
866 
867  for(;;) /* wait until reset */
868  {
869  __NOP();
870  }
871 }
872 
873 /*@} end of CMSIS_Core_NVICFunctions */
874 
875 
876 
877 /* ################################## SysTick function ############################################ */
878 /**
879  \ingroup CMSIS_Core_FunctionInterface
880  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
881  \brief Functions that configure the System.
882  @{
883  */
884 
885 #if (__Vendor_SysTickConfig == 0U)
886 
887 /**
888  \brief System Tick Configuration
889  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
890  Counter is in free running mode to generate periodic interrupts.
891  \param [in] ticks Number of ticks between two interrupts.
892  \return 0 Function succeeded.
893  \return 1 Function failed.
894  \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
895  function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
896  must contain a vendor-specific implementation of this function.
897  */
898 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
899 {
900  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
901  {
902  return (1UL); /* Reload value impossible */
903  }
904 
905  SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
906  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
907  SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
910  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
911  return (0UL); /* Function successful */
912 }
913 
914 #endif
915 
916 /*@} end of CMSIS_Core_SysTickFunctions */
917 
918 
919 
920 
921 #ifdef __cplusplus
922 }
923 #endif
924 
925 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
926 
927 #endif /* __CMSIS_GENERIC */
CMSIS Cortex-M Core Function Access Header File.
IRQn
Definition: cc2538_cm3.h:64
15 System Tick Interrupt
Definition: cc2538_cm3.h:75
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_cm0plus.h:471
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_cm0.h:362
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_cm0plus.h:533
Structure type to access the System Control Block (SCB).
Definition: core_cm0.h:389
CMSIS Cortex-M Core Instruction Access Header File.
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_cm0.h:701
#define SysTick_CTRL_TICKINT_Msk
Definition: core_cm0plus.h:536
#define SCB
Definition: core_cm0plus.h:699
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Disable External Interrupt.
Definition: core_cm0.h:653
Structure type to access the System Timer (SysTick).
Definition: core_cm0.h:496
__STATIC_INLINE void NVIC_SystemReset(void)
System Reset.
Definition: core_cm0.h:743
Union type to access the Application Program Status Register (APSR).
Definition: core_cm0.h:247
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Enable External Interrupt.
Definition: core_cm0.h:642
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_cm0.h:666
__STATIC_INLINE uint32_t NVIC_IsIRQEnabled(IRQn_Type IRQn)
Get External Interrupt Enable State.
Definition: core_cm0.h:631
#define SysTick
Definition: core_cm0plus.h:700
__STATIC_INLINE void __NOP(void)
No Operation.
Definition: cmsis_gcc.h:373
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
System Tick Configuration.
Definition: core_cm0.h:782
Union type to access the Control Registers (CONTROL).
Definition: core_cm0.h:334
#define NVIC
Definition: core_cm0plus.h:701
#define SysTick_LOAD_RELOAD_Msk
Definition: core_cm0plus.h:543
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_cm0.h:677
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_cm0.h:688
__STATIC_INLINE void __DSB(void)
Data Synchronization Barrier.
Definition: cmsis_gcc.h:427
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_cm0.h:277
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_cm0.h:295
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_cm0.h:725
#define SysTick_CTRL_ENABLE_Msk
Definition: core_cm0plus.h:539
uint32_t nPRIV
Definition: core_cm0plus.h:349
#define __NVIC_PRIO_BITS
Number of Bits used for Priority Levels.
Definition: cc2538_cm3.h:126
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_cm0plus.h:481