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cc13x0-cc26x0-cm3.h
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1 /*
2  * Template:
3  * Copyright (c) 2012 ARM LIMITED
4  * All rights reserved.
5  *
6  * CC13xx-CC26xx:
7  * Copyright (c) 2017, George Oikonomou - http://www.spd.gr
8  * All rights reserved.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  *
14  * 1. Redistributions of source code must retain the above copyright
15  * notice, this list of conditions and the following disclaimer.
16  * 2. Redistributions in binary form must reproduce the above copyright
17  * notice, this list of conditions and the following disclaimer in the
18  * documentation and/or other materials provided with the distribution.
19  * 3. Neither the name of the copyright holder nor the names of its
20  * contributors may be used to endorse or promote products derived
21  * from this software without specific prior written permission.
22  *
23  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
24  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
25  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
26  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
27  * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
28  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
32  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
34  * OF THE POSSIBILITY OF SUCH DAMAGE.
35  */
36 /*---------------------------------------------------------------------------*/
37 /**
38  * \addtogroup cc26xx
39  * @{
40  *
41  * \defgroup cc26xx-cm3 CC13xx/CC26xx CMSIS
42  *
43  * CC13xx/CC26xx Cortex-M3 CMSIS definitions
44  * @{
45  *
46  * \file
47  * CMSIS Cortex-M3 core peripheral access layer header file for CC13xx/CC26xx
48  */
49 /*---------------------------------------------------------------------------*/
50 #ifndef CC13XX_CC26XX_CM3_H_
51 #define CC13XX_CC26XX_CM3_H_
52 /*---------------------------------------------------------------------------*/
53 /**
54  * \name Interrupt Number Definition
55  * @{
56  */
58  /* Cortex-M3 Processor Exceptions */
59  CC13XX_CC26XX_CM3_EXCEPTION_RESET = -15, /**< 1 Reset */
60  CC13XX_CC26XX_CM3_EXCEPTION_NMI = -14, /**< 2 NMI */
61  CC13XX_CC26XX_CM3_EXCEPTION_HARD_FAULT = -13, /**< 3 Hard fault */
62  CC13XX_CC26XX_CM3_EXCEPTION_MPU_FAULT = -12, /**< 4 MPU fault */
63  CC13XX_CC26XX_CM3_EXCEPTION_BUS_FAULT = -11, /**< 5 Bus fault */
64  CC13XX_CC26XX_CM3_EXCEPTION_USAGE_FAULT = -10, /**< 6 Usage fault */
65  CC13XX_CC26XX_CM3_EXCEPTION_SV_CALL = -5, /**< 11 SVCall */
66  CC13XX_CC26XX_CM3_EXCEPTION_DEBUG_MON = -4, /**< 12 Debug monitor */
67  CC13XX_CC26XX_CM3_EXCEPTION_PEND_SV = -2, /**< 14 PendSV */
68  CC13XX_CC26XX_CM3_EXCEPTION_SYS_TICK = -1, /**< 15 SysTick */
69 
70  /* CC13xx/CC26xx interrupts */
71  CC13XX_CC26XX_CM3_IRQ_EDGE_DETECT = 0, /**< 16 AON edge detect */
72  CC13XX_CC26XX_CM3_EXCEPTION_I2C = 1, /**< 17 I2C */
73  CC13XX_CC26XX_CM3_EXCEPTION_RF_CPE1 = 2, /**< 18 RF Command and Packet Engine 1 */
74  CC13XX_CC26XX_CM3_EXCEPTION_AON_SPI_SLAVE = 3, /**< 19 AON SpiSplave Rx, Tx and CS */
75  CC13XX_CC26XX_CM3_EXCEPTION_AON_RTC = 4, /**< 20 AON RTC */
76  CC13XX_CC26XX_CM3_EXCEPTION_UART0 = 5, /**< 21 UART0 Rx and Tx */
77  CC13XX_CC26XX_CM3_EXCEPTION_AON_AUX_SWEV0 = 6, /**< 22 Sensor Controller software event 0, through AON domain*/
78  CC13XX_CC26XX_CM3_EXCEPTION_SSI0 = 7, /**< 23 SSI0 Rx and Tx */
79  CC13XX_CC26XX_CM3_EXCEPTION_SSI1 = 8, /**< 24 SSI1 Rx and Tx */
80  CC13XX_CC26XX_CM3_EXCEPTION_RF_CPE0 = 9, /**< 25 RF Command and Packet Engine 0 */
81  CC13XX_CC26XX_CM3_EXCEPTION_RF_HW = 10, /**< 26 RF Core Hardware */
82  CC13XX_CC26XX_CM3_EXCEPTION_RF_CMD_ACK = 11, /**< 27 RF Core Command Acknowledge */
83  CC13XX_CC26XX_CM3_EXCEPTION_I2S = 12, /**< 28 I2S */
84  CC13XX_CC26XX_CM3_EXCEPTION_AON_AUX_SWEV1 = 13, /**< 29 Sensor Controller software event 1, through AON domain*/
85  CC13XX_CC26XX_CM3_EXCEPTION_WATCHDOG = 14, /**< 30 Watchdog timer */
86  CC13XX_CC26XX_CM3_EXCEPTION_GPTIMER_0A = 15, /**< 31 Timer 0 subtimer A */
87  CC13XX_CC26XX_CM3_EXCEPTION_GPTIMER_0B = 16, /**< 32 Timer 0 subtimer B */
88  CC13XX_CC26XX_CM3_EXCEPTION_GPTIMER_1A = 17, /**< 33 Timer 1 subtimer A */
89  CC13XX_CC26XX_CM3_EXCEPTION_GPTIMER_1B = 18, /**< 34 Timer 1 subtimer B */
90  CC13XX_CC26XX_CM3_EXCEPTION_GPTIMER_2A = 19, /**< 35 Timer 2 subtimer A */
91  CC13XX_CC26XX_CM3_EXCEPTION_GPTIMER_2B = 20, /**< 36 Timer 2 subtimer B */
92  CC13XX_CC26XX_CM3_EXCEPTION_GPTIMER_3A = 21, /**< 37 Timer 3 subtimer A */
93  CC13XX_CC26XX_CM3_EXCEPTION_GPTIMER_3B = 22, /**< 38 Timer 3 subtimer B */
94  CC13XX_CC26XX_CM3_EXCEPTION_CRYPTO = 23, /**< 39 Crypto Core Result available */
95  CC13XX_CC26XX_CM3_EXCEPTION_UDMA = 24, /**< 40 uDMA Software */
96  CC13XX_CC26XX_CM3_EXCEPTION_UDMA_ERR = 25, /**< 41 uDMA Error */
97  CC13XX_CC26XX_CM3_EXCEPTION_FLASH_CTRL = 26, /**< 42 Flash controller */
98  CC13XX_CC26XX_CM3_EXCEPTION_SW0 = 27, /**< 43 Software Event 0 */
99  CC13XX_CC26XX_CM3_EXCEPTION_AUX_COM_EVENT = 28, /**< 44 AUX combined event, directly to MCU domain*/
100  CC13XX_CC26XX_CM3_EXCEPTION_AON_PRG0 = 29, /**< 45 AON programmable 0 */
101  CC13XX_CC26XX_CM3_EXCEPTION_PROG = 30, /**< 46 Dynamic Programmable interrupt (default source: PRCM)*/
102  CC13XX_CC26XX_CM3_EXCEPTION_AUX_COMPA = 31, /**< 47 AUX Comparator A */
103  CC13XX_CC26XX_CM3_EXCEPTION_AUX_ADC = 32, /**< 48 AUX ADC IRQ */
104  CC13XX_CC26XX_CM3_EXCEPTION_TRNG = 33, /**< 49 TRNG event */
105 } cc13xx_cc26xx_cm3_irq_t;
106 
107 typedef cc13xx_cc26xx_cm3_irq_t IRQn_Type;
108 
109 #define SysTick_IRQn CC13XX_CC26XX_CM3_EXCEPTION_SYS_TICK
110 /** @} */
111 /*---------------------------------------------------------------------------*/
112 /** \name Processor and Core Peripheral Section
113  * @{
114  */
115 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
116 #define __MPU_PRESENT 1 /**< MPU present or not */
117 #define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */
118 #define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
119 /** @} */
120 /*---------------------------------------------------------------------------*/
121 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
122 /*---------------------------------------------------------------------------*/
123 #endif /* CC13XX_CC26XX_CM3_H_ */
124 /*---------------------------------------------------------------------------*/
125 /**
126  * @}
127  * @}
128  */
19 AON SpiSplave Rx, Tx and CS
CMSIS Cortex-M3 Core Peripheral Access Layer Header File.
39 Crypto Core Result available
29 Sensor Controller software event 1, through AON domain
46 Dynamic Programmable interrupt (default source: PRCM)
22 Sensor Controller software event 0, through AON domain
44 AUX combined event, directly to MCU domain
25 RF Command and Packet Engine 0
18 RF Command and Packet Engine 1
27 RF Core Command Acknowledge
cc13xx_cc26xx_cm3_irq_e