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pka.h
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1/*
2 * Original file:
3 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
4 * All rights reserved.
5 *
6 * Port to Contiki:
7 * Copyright (c) 2014 Andreas Dröscher <contiki@anticat.ch>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * 3. Neither the name of the copyright holder nor the names of its
19 * contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
26 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
31 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
33 * OF THE POSSIBILITY OF SUCH DAMAGE.
34 */
35/**
36 * \addtogroup cc2538
37 * @{
38 *
39 * \defgroup cc2538-pka cc2538 PKA engine
40 *
41 * Driver for the cc2538 PKA engine
42 * @{
43 *
44 * \file
45 * Header file for the cc2538 PKA engine driver
46 */
47#ifndef PKA_H_
48#define PKA_H_
49
50#include "contiki.h"
51#include <stdint.h>
52#include <stdbool.h>
53
54/*---------------------------------------------------------------------------*/
55/** \name PKA memory
56 * @{
57 */
58#define PKA_RAM_BASE 0x44006000 /**< PKA Memory Address */
59#define PKA_RAM_SIZE 0x800 /**< PKA Memory Size */
60#define PKA_MAX_CURVE_SIZE 12 /**< Define for the maximum curve
61 size supported by the PKA module
62 in 32 bit word. */
63#define PKA_MAX_LEN 12 /**< Define for the maximum length of
64 the big number supported by the
65 PKA module in 32 bit word. */
66/** @} */
67/*---------------------------------------------------------------------------*/
68/** \name PKA register offsets
69 * @{
70 */
71#define PKA_APTR 0x44004000 /**< PKA vector A address During
72 execution of basic PKCP
73 operations, this register is
74 double buffered and can be
75 written with a new value for the
76 next operation; when not
77 written, the value remains
78 intact. During the execution of
79 sequencer-controlled complex
80 operations, this register may
81 not be written and its value is
82 undefined at the conclusion of
83 the operation. The driver
84 software cannot rely on the
85 written value to remain intact. */
86#define PKA_BPTR 0x44004004 /**< PKA vector B address During
87 execution of basic PKCP
88 operations, this register is
89 double buffered and can be
90 written with a new value for the
91 next operation; when not
92 written, the value remains
93 intact. During the execution of
94 sequencer-controlled complex
95 operations, this register may
96 not be written and its value is
97 undefined at the conclusion of
98 the operation. The driver
99 software cannot rely on the
100 written value to remain intact. */
101#define PKA_CPTR 0x44004008 /**< PKA vector C address During
102 execution of basic PKCP
103 operations, this register is
104 double buffered and can be
105 written with a new value for the
106 next operation; when not
107 written, the value remains
108 intact. During the execution of
109 sequencer-controlled complex
110 operations, this register may
111 not be written and its value is
112 undefined at the conclusion of
113 the operation. The driver
114 software cannot rely on the
115 written value to remain intact. */
116#define PKA_DPTR 0x4400400C /**< PKA vector D address During
117 execution of basic PKCP
118 operations, this register is
119 double buffered and can be
120 written with a new value for the
121 next operation; when not
122 written, the value remains
123 intact. During the execution of
124 sequencer-controlled complex
125 operations, this register may
126 not be written and its value is
127 undefined at the conclusion of
128 the operation. The driver
129 software cannot rely on the
130 written value to remain intact. */
131#define PKA_ALENGTH 0x44004010 /**< PKA vector A length During
132 execution of basic PKCP
133 operations, this register is
134 double buffered and can be
135 written with a new value for the
136 next operation; when not
137 written, the value remains
138 intact. During the execution of
139 sequencer-controlled complex
140 operations, this register may
141 not be written and its value is
142 undefined at the conclusion of
143 the operation. The driver
144 software cannot rely on the
145 written value to remain intact. */
146#define PKA_BLENGTH 0x44004014 /**< PKA vector B length During
147 execution of basic PKCP
148 operations, this register is
149 double buffered and can be
150 written with a new value for the
151 next operation; when not
152 written, the value remains
153 intact. During the execution of
154 sequencer-controlled complex
155 operations, this register may
156 not be written and its value is
157 undefined at the conclusion of
158 the operation. The driver
159 software cannot rely on the
160 written value to remain intact. */
161#define PKA_SHIFT 0x44004018 /**< PKA bit shift value For basic
162 PKCP operations, modifying the
163 contents of this register is
164 made impossible while the
165 operation is being performed.
166 For the ExpMod-variable and
167 ExpMod-CRT operations, this
168 register is used to indicate the
169 number of odd powers to use
170 (directly as a value in the
171 range 1-16). For the ModInv and
172 ECC operations, this register is
173 used to hold a completion code. */
174#define PKA_FUNCTION 0x4400401C /**< PKA function This register
175 contains the control bits to
176 start basic PKCP as well as
177 complex sequencer operations.
178 The run bit can be used to poll
179 for the completion of the
180 operation. Modifying bits [11:0]
181 is made impossible during the
182 execution of a basic PKCP
183 operation. During the execution
184 of sequencer-controlled complex
185 operations, this register is
186 modified; the run and stall
187 result bits are set to zero at
188 the conclusion, but other bits
189 are undefined. Attention:
190 Continuously reading this
191 register to poll the run bit is
192 not allowed when executing
193 complex sequencer operations
194 (the sequencer cannot access the
195 PKCP when this is done). Leave
196 at least one sysclk cycle
197 between poll operations. */
198#define PKA_COMPARE 0x44004020 /**< PKA compare result This
199 register provides the result of
200 a basic PKCP compare operation.
201 It is updated when the run bit
202 in the PKA_FUNCTION register is
203 reset at the end of that
204 operation. Status after a
205 complex sequencer operation is
206 unknown */
207#define PKA_MSW 0x44004024 /**< PKA most-significant-word of
208 result vector This register
209 indicates the (word) address in
210 the PKA RAM where the most
211 significant nonzero 32-bit word
212 of the result is stored. Should
213 be ignored for modulo
214 operations. For basic PKCP
215 operations, this register is
216 updated when the run bit in the
217 PKA_FUNCTION register is reset
218 at the end of the operation. For
219 the complex-sequencer controlled
220 operations, updating of the
221 final value matching the actual
222 result is done near the end of
223 the operation; note that the
224 result is only meaningful if no
225 errors were detected and that
226 for ECC operations, the PKA_MSW
227 register will provide
228 information for the x-coordinate
229 of the result point only. */
230#define PKA_DIVMSW 0x44004028 /**< PKA most-significant-word of
231 divide remainder This register
232 indicates the (32-bit word)
233 address in the PKA RAM where the
234 most significant nonzero 32-bit
235 word of the remainder result for
236 the basic divide and modulo
237 operations is stored. Bits [4:0]
238 are loaded with the bit number
239 of the most-significant nonzero
240 bit in the most-significant
241 nonzero word when MS one control
242 bit is set. For divide, modulo,
243 and MS one reporting, this
244 register is updated when the RUN
245 bit in the PKA_FUNCTION register
246 is reset at the end of the
247 operation. For the complex
248 sequencer controlled operations,
249 updating of bits [4:0] of this
250 register with the
251 most-significant bit location of
252 the actual result is done near
253 the end of the operation. The
254 result is meaningful only if no
255 errors were detected and that
256 for ECC operations; the
257 PKA_DIVMSW register provides
258 information for the x-coordinate
259 of the result point only. */
260#define PKA_SEQ_CTRL 0x440040C8 /**< PKA sequencer control and
261 status register The sequencer is
262 interfaced with the outside
263 world through a single control
264 and status register. With the
265 exception of bit [31], the
266 actual use of bits in the
267 separate sub-fields of this
268 register is determined by the
269 sequencer firmware. This
270 register need only be accessed
271 when the sequencer program is
272 stored in RAM. The reset value
273 of the RESTE bit depends upon
274 the option chosen for sequencer
275 program storage. */
276#define PKA_OPTIONS 0x440040F4 /**< PKA hardware options register
277 This register provides the host
278 with a means to determine the
279 hardware configuration
280 implemented in this PKA engine,
281 focused on options that have an
282 effect on software interacting
283 with the module. Note: (32 x
284 (1st LNME nr. of PEs + 1st LNME
285 FIFO RAM depth - 10)) equals the
286 maximum modulus vector length
287 (in bits) that can be handled by
288 the modular exponentiation and
289 ECC operations executed on a PKA
290 engine that includes an LNME. */
291#define PKA_SW_REV 0x440040F8 /**< PKA firmware revision and
292 capabilities register This
293 register allows the host access
294 to the internal firmware
295 revision number of the PKA
296 Engine for software driver
297 matching and diagnostic
298 purposes. This register also
299 contains a field that encodes
300 the capabilities of the embedded
301 firmware. The PKA_SW_REV
302 register is written by the
303 firmware within a few clock
304 cycles after starting up that
305 firmware. The hardware reset
306 value is zero, indicating that
307 the information has not been
308 written yet. */
309#define PKA_REVISION 0x440040FC /**< PKA hardware revision register
310 This register allows the host
311 access to the hardware revision
312 number of the PKA engine for
313 software driver matching and
314 diagnostic purposes. It is
315 always located at the highest
316 address in the access space of
317 the module and contains an
318 encoding of the EIP number (with
319 its complement as signature) for
320 recognition of the hardware
321 module. */
322/** @} */
323/*---------------------------------------------------------------------------*/
324/** \name PKA_APTR register registers bit fields
325 * @{
326 */
327#define PKA_APTR_APTR_M 0x000007FF /**< This register specifies the
328 location of vector A within the
329 PKA RAM. Vectors are identified
330 through the location of their
331 least-significant 32-bit word.
332 Note that bit [0] must be zero
333 to ensure that the vector starts
334 at an 8-byte boundary. */
335#define PKA_APTR_APTR_S 0
336/** @} */
337/*---------------------------------------------------------------------------*/
338/** \name PKA_BPTR register registers bit fields
339 * @{
340 */
341#define PKA_BPTR_BPTR_M 0x000007FF /**< This register specifies the
342 location of vector B within the
343 PKA RAM. Vectors are identified
344 through the location of their
345 least-significant 32-bit word.
346 Note that bit [0] must be zero
347 to ensure that the vector starts
348 at an 8-byte boundary. */
349#define PKA_BPTR_BPTR_S 0
350/** @} */
351/*---------------------------------------------------------------------------*/
352/** \name PKA_CPTR register registers bit fields
353 * @{
354 */
355#define PKA_CPTR_CPTR_M 0x000007FF /**< This register specifies the
356 location of vector C within the
357 PKA RAM. Vectors are identified
358 through the location of their
359 least-significant 32-bit word.
360 Note that bit [0] must be zero
361 to ensure that the vector starts
362 at an 8-byte boundary. */
363#define PKA_CPTR_CPTR_S 0
364/** @} */
365/*---------------------------------------------------------------------------*/
366/** \name PKA_DPTR register registers bit fields
367 * @{
368 */
369#define PKA_DPTR_DPTR_M 0x000007FF /**< This register specifies the
370 location of vector D within the
371 PKA RAM. Vectors are identified
372 through the location of their
373 least-significant 32-bit word.
374 Note that bit [0] must be zero
375 to ensure that the vector starts
376 at an 8-byte boundary. */
377#define PKA_DPTR_DPTR_S 0
378/** @} */
379/*---------------------------------------------------------------------------*/
380/** \name PKA_ALENGTH register registers bit fields
381 * @{
382 */
383#define PKA_ALENGTH_ALENGTH_M 0x000001FF /**< This register specifies the
384 length (in 32-bit words) of
385 Vector A. */
386#define PKA_ALENGTH_ALENGTH_S 0
387/** @} */
388/*---------------------------------------------------------------------------*/
389/** \name PKA_BLENGTH register registers bit fields
390 * @{
391 */
392#define PKA_BLENGTH_BLENGTH_M 0x000001FF /**< This register specifies the
393 length (in 32-bit words) of
394 Vector B. */
395#define PKA_BLENGTH_BLENGTH_S 0
396/** @} */
397/*---------------------------------------------------------------------------*/
398/** \name PKA_SHIFT register registers bit fields
399 * @{
400 */
401#define PKA_SHIFT_NUM_BITS_TO_SHIFT_M \
402 0x0000001F /**< This register specifies the
403 number of bits to shift the
404 input vector (in the range 0-31)
405 during a Rshift or Lshift
406 operation. */
407
408#define PKA_SHIFT_NUM_BITS_TO_SHIFT_S 0
409/** @} */
410/*---------------------------------------------------------------------------*/
411/** \name PKA_FUNCTION register registers bit fields
412 * @{
413 */
414#define PKA_FUNCTION_STALL_RESULT \
415 0x01000000 /**< When written with a 1b,
416 updating of the PKA_COMPARE,
417 PKA_MSW and PKA_DIVMSW
418 registers, as well as resetting
419 the run bit is stalled beyond
420 the point that a running
421 operation is actually finished.
422 Use this to allow software
423 enough time to read results from
424 a previous operation when the
425 newly started operation is known
426 to take only a short amount of
427 time. If a result is waiting,
428 the result registers is updated
429 and the run bit is reset in the
430 clock cycle following writing
431 the stall result bit back to 0b.
432 The Stall result function may
433 only be used for basic PKCP
434 operations. */
435
436#define PKA_FUNCTION_STALL_RESULT_M \
437 0x01000000
438#define PKA_FUNCTION_STALL_RESULT_S 24
439#define PKA_FUNCTION_RUN 0x00008000 /**< The host sets this bit to
440 instruct the PKA module to begin
441 processing the basic PKCP or
442 complex sequencer operation.
443 This bit is reset low
444 automatically when the operation
445 is complete. The complement of
446 this bit is output as
447 interrupts[1]. After a reset,
448 the run bit is always set to 1b.
449 Depending on the option, program
450 ROM or program RAM, the
451 following applies: Program ROM -
452 The first sequencer instruction
453 sets the bit to 0b. This is done
454 immediately after the hardware
455 reset is released. Program RAM -
456 The sequencer must set the bit
457 to 0b. As a valid firmware may
458 not have been loaded, the
459 sequencer is held in software
460 reset after the hardware reset
461 is released (the reset bit in
462 PKA_SEQ_CRTL is set to 1b).
463 After the FW image is loaded and
464 the Reset bit is cleared, the
465 sequencer starts to execute the
466 FW. The first instruction clears
467 the run bit. In both cases a few
468 clock cycles are needed before
469 the first instruction is
470 executed and the run bit state
471 has been propagated. */
472#define PKA_FUNCTION_RUN_M 0x00008000
473#define PKA_FUNCTION_RUN_S 15
474#define PKA_FUNCTION_SEQUENCER_OPERATIONS_M \
475 0x00007000 /**< These bits select the complex
476 sequencer operation to perform:
477 000b: None 001b: ExpMod-CRT
478 010b: ExpMod-ACT4 (compatible
479 with EIP2315) 011b: ECC-ADD (if
480 available in firmware, otherwise
481 reserved) 100b: ExpMod-ACT2
482 (compatible with EIP2316) 101b:
483 ECC-MUL (if available in
484 firmware, otherwise reserved)
485 110b: ExpMod-variable 111b:
486 ModInv (if available in
487 firmware, otherwise reserved)
488 The encoding of these operations
489 is determined by sequencer
490 firmware. */
491
492#define PKA_FUNCTION_SEQUENCER_OPERATIONS_S 12
493#define PKA_FUNCTION_COPY 0x00000800 /**< Perform copy operation */
494#define PKA_FUNCTION_COPY_M 0x00000800
495#define PKA_FUNCTION_COPY_S 11
496#define PKA_FUNCTION_COMPARE 0x00000400 /**< Perform compare operation */
497#define PKA_FUNCTION_COMPARE_M 0x00000400
498#define PKA_FUNCTION_COMPARE_S 10
499#define PKA_FUNCTION_MODULO 0x00000200 /**< Perform modulo operation */
500#define PKA_FUNCTION_MODULO_M 0x00000200
501#define PKA_FUNCTION_MODULO_S 9
502#define PKA_FUNCTION_DIVIDE 0x00000100 /**< Perform divide operation */
503#define PKA_FUNCTION_DIVIDE_M 0x00000100
504#define PKA_FUNCTION_DIVIDE_S 8
505#define PKA_FUNCTION_LSHIFT 0x00000080 /**< Perform left shift operation */
506#define PKA_FUNCTION_LSHIFT_M 0x00000080
507#define PKA_FUNCTION_LSHIFT_S 7
508#define PKA_FUNCTION_RSHIFT 0x00000040 /**< Perform right shift operation */
509#define PKA_FUNCTION_RSHIFT_M 0x00000040
510#define PKA_FUNCTION_RSHIFT_S 6
511#define PKA_FUNCTION_SUBTRACT 0x00000020 /**< Perform subtract operation */
512#define PKA_FUNCTION_SUBTRACT_M 0x00000020
513#define PKA_FUNCTION_SUBTRACT_S 5
514#define PKA_FUNCTION_ADD 0x00000010 /**< Perform add operation */
515#define PKA_FUNCTION_ADD_M 0x00000010
516#define PKA_FUNCTION_ADD_S 4
517#define PKA_FUNCTION_MS_ONE 0x00000008 /**< Loads the location of the Most
518 Significant one bit within the
519 result word indicated in the
520 PKA_MSW register into bits [4:0]
521 of the PKA_DIVMSW register - can
522 only be used with basic PKCP
523 operations, except for Divide,
524 Modulo and Compare. */
525#define PKA_FUNCTION_MS_ONE_M 0x00000008
526#define PKA_FUNCTION_MS_ONE_S 3
527#define PKA_FUNCTION_ADDSUB 0x00000002 /**< Perform combined add/subtract
528 operation */
529#define PKA_FUNCTION_ADDSUB_M 0x00000002
530#define PKA_FUNCTION_ADDSUB_S 1
531#define PKA_FUNCTION_MULTIPLY 0x00000001 /**< Perform multiply operation */
532#define PKA_FUNCTION_MULTIPLY_M 0x00000001
533#define PKA_FUNCTION_MULTIPLY_S 0
534#define PKA_FUNCTION_ECCADD 0x00003000
535#define PKA_FUNCTION_ECCMUL 0x00005000
536#define PKA_FUNCTION_INVMOD 0x00007000
537
538/** @} */
539/*---------------------------------------------------------------------------*/
540/** \name PKA_COMPARE register registers bit fields
541 * @{
542 */
543#define PKA_COMPARE_A_GREATER_THAN_B \
544 0x00000004 /**< Vector_A is greater than
545 Vector_B */
546
547#define PKA_COMPARE_A_GREATER_THAN_B_M \
548 0x00000004
549#define PKA_COMPARE_A_GREATER_THAN_B_S 2
550#define PKA_COMPARE_A_LESS_THAN_B \
551 0x00000002 /**< Vector_A is less than Vector_B */
552
553#define PKA_COMPARE_A_LESS_THAN_B_M \
554 0x00000002
555#define PKA_COMPARE_A_LESS_THAN_B_S 1
556#define PKA_COMPARE_A_EQUALS_B 0x00000001 /**< Vector_A is equal to Vector_B */
557#define PKA_COMPARE_A_EQUALS_B_M \
558 0x00000001
559#define PKA_COMPARE_A_EQUALS_B_S 0
560/** @} */
561/*---------------------------------------------------------------------------*/
562/** \name PKA_SHIFT result values
563 * @{
564 */
565#define PKA_SHIFT_SUCCESS 0
566#define PKA_SHIFT_POINT_AT_INFINITY 7
567#define PKA_SHIFT_ERROR 31
568/** @} */
569/*---------------------------------------------------------------------------*/
570/** \name PKA_MSW register registers bit fields
571 * @{
572 */
573#define PKA_MSW_RESULT_IS_ZERO 0x00008000 /**< The result vector is all
574 zeroes, ignore the address
575 returned in bits [10:0] */
576#define PKA_MSW_RESULT_IS_ZERO_M \
577 0x00008000
578#define PKA_MSW_RESULT_IS_ZERO_S 15
579#define PKA_MSW_MSW_ADDRESS_M 0x000007FF /**< Address of the most-significant
580 nonzero 32-bit word of the
581 result vector in PKA RAM */
582#define PKA_MSW_MSW_ADDRESS_S 0
583/** @} */
584/*---------------------------------------------------------------------------*/
585/** \name PKA_DIVMSW register registers bit fields
586 * @{
587 */
588#define PKA_DIVMSW_RESULT_IS_ZERO \
589 0x00008000 /**< The result vector is all
590 zeroes, ignore the address
591 returned in bits [10:0] */
592
593#define PKA_DIVMSW_RESULT_IS_ZERO_M \
594 0x00008000
595#define PKA_DIVMSW_RESULT_IS_ZERO_S 15
596#define PKA_DIVMSW_MSW_ADDRESS_M \
597 0x000007FF /**< Address of the most significant
598 nonzero 32-bit word of the
599 remainder result vector in PKA
600 RAM */
601
602#define PKA_DIVMSW_MSW_ADDRESS_S 0
603/** @} */
604/*---------------------------------------------------------------------------*/
605/** \name PKA_SEQ_CTRL register registers bit fields
606 * @{
607 */
608#define PKA_SEQ_CTRL_RESET 0x80000000 /**< Option program ROM: Reset value
609 = 0. Read/Write, reset value 0b
610 (ZERO). Writing 1b resets the
611 sequencer, write to 0b to
612 restart operations again. As the
613 reset value is 0b, the sequencer
614 will automatically start
615 operations executing from
616 program ROM. This bit should
617 always be written with zero and
618 ignored when reading this
619 register. Option Program RAM:
620 Reset value =1. Read/Write,
621 reset value 1b (ONE). When 1b,
622 the sequencer is held in a reset
623 state and the PKA_PROGRAM area
624 is accessible for loading the
625 sequencer program (while the
626 PKA_DATA_RAM is inaccessible),
627 write to 0b to (re)start
628 sequencer operations and disable
629 PKA_PROGRAM area accessibility
630 (also enables the PKA_DATA_RAM
631 accesses). Resetting the
632 sequencer (in order to load
633 other firmware) should only be
634 done when the PKA Engine is not
635 performing any operations (i.e.
636 the run bit in the PKA_FUNCTION
637 register should be zero). */
638#define PKA_SEQ_CTRL_RESET_M 0x80000000
639#define PKA_SEQ_CTRL_RESET_S 31
640#define PKA_SEQ_CTRL_SEQUENCER_STATUS_M \
641 0x0000FF00 /**< These read-only bits can be
642 used by the sequencer to
643 communicate status to the
644 outside world. Bit [8] is also
645 used as sequencer interrupt,
646 with the complement of this bit
647 ORed into the run bit in
648 PKA_FUNCTION. This field should
649 always be written with zeroes
650 and ignored when reading this
651 register. */
652
653#define PKA_SEQ_CTRL_SEQUENCER_STATUS_S 8
654#define PKA_SEQ_CTRL_SW_CONTROL_STATUS_M \
655 0x000000FF /**< These bits can be used by
656 software to trigger sequencer
657 operations. External logic can
658 set these bits by writing 1b,
659 cannot reset them by writing 0b.
660 The sequencer can reset these
661 bits by writing 0b, cannot set
662 them by writing 1b. Setting the
663 run bit in PKA_FUNCTION together
664 with a nonzero sequencer
665 operations field automatically
666 sets bit [0] here. This field
667 should always be written with
668 zeroes and ignored when reading
669 this register. */
670
671#define PKA_SEQ_CTRL_SW_CONTROL_STATUS_S 0
672/** @} */
673/*---------------------------------------------------------------------------*/
674/** \name PKA_OPTIONS register registers bit fields
675 * @{
676 */
677#define PKA_OPTIONS_FIRST_LNME_FIFO_DEPTH_M \
678 0xFF000000 /**< Number of words in the first
679 LNME's FIFO RAM Should be
680 ignored if LNME configuration is
681 0. The contents of this field
682 indicate the actual depth as
683 selected by the LNME FIFO RAM
684 size strap input, fifo_size_sel.
685 Note: Reset value is undefined */
686
687#define PKA_OPTIONS_FIRST_LNME_FIFO_DEPTH_S 24
688#define PKA_OPTIONS_FIRST_LNME_NR_OF_PES_M \
689 0x003F0000 /**< Number of processing elements
690 in the pipeline of the first
691 LNME Should be ignored if LNME
692 configuration is 0. Note: Reset
693 value is undefined. */
694
695#define PKA_OPTIONS_FIRST_LNME_NR_OF_PES_S 16
696#define PKA_OPTIONS_MMM3A 0x00001000 /**< Reserved for a future
697 functional extension to the LNME
698 Always 0b */
699#define PKA_OPTIONS_MMM3A_M 0x00001000
700#define PKA_OPTIONS_MMM3A_S 12
701#define PKA_OPTIONS_INT_MASKING 0x00000800 /**< Value 0b indicates that the
702 main interrupt output (bit [1]
703 of the interrupts output bus) is
704 the direct complement of the run
705 bit in the PKA_CONTROL register,
706 value 1b indicates that
707 interrupt masking logic is
708 present for this output. Note:
709 Reset value is undefined */
710#define PKA_OPTIONS_INT_MASKING_M \
711 0x00000800
712#define PKA_OPTIONS_INT_MASKING_S 11
713#define PKA_OPTIONS_PROTECTION_OPTION_M \
714 0x00000700 /**< Value 0 indicates no additional
715 protection against side channel
716 attacks, value 1 indicates the
717 SCAP option, value 3 indicates
718 the PROT option; other values
719 are reserved. Note: Reset value
720 is undefined */
721
722#define PKA_OPTIONS_PROTECTION_OPTION_S 8
723#define PKA_OPTIONS_PROGRAM_RAM 0x00000080 /**< Value 1b indicates sequencer
724 program storage in RAM, value 0b
725 in ROM. Note: Reset value is
726 undefined */
727#define PKA_OPTIONS_PROGRAM_RAM_M \
728 0x00000080
729#define PKA_OPTIONS_PROGRAM_RAM_S 7
730#define PKA_OPTIONS_SEQUENCER_CONFIGURATION_M \
731 0x00000060 /**< Value 1 indicates a standard
732 sequencer; other values are
733 reserved. */
734
735#define PKA_OPTIONS_SEQUENCER_CONFIGURATION_S 5
736#define PKA_OPTIONS_LNME_CONFIGURATION_M \
737 0x0000001C /**< Value 0 indicates NO LNME,
738 value 1 indicates one standard
739 LNME (with alpha = 32, beta =
740 8); other values reserved. Note:
741 Reset value is undefined */
742
743#define PKA_OPTIONS_LNME_CONFIGURATION_S 2
744#define PKA_OPTIONS_PKCP_CONFIGURATION_M \
745 0x00000003 /**< Value 1 indicates a PKCP with a
746 16x16 multiplier, value 2
747 indicates a PKCP with a 32x32
748 multiplier, other values
749 reserved. Note: Reset value is
750 undefined. */
751
752#define PKA_OPTIONS_PKCP_CONFIGURATION_S 0
753/** @} */
754/*---------------------------------------------------------------------------*/
755/** \name PKA_SW_REV register registers bit fields
756 * @{
757 */
758#define PKA_SW_REV_FW_CAPABILITIES_M \
759 0xF0000000 /**< 4-bit binary encoding for the
760 functionality implemented in the
761 firmware. Value 0 indicates
762 basic ModExp with/without CRT.
763 Value 1 adds Modular Inversion,
764 value 2 adds Modular Inversion
765 and ECC operations. Values 3-15
766 are reserved. */
767
768#define PKA_SW_REV_FW_CAPABILITIES_S 28
769#define PKA_SW_REV_MAJOR_FW_REVISION_M \
770 0x0F000000 /**< 4-bit binary encoding of the
771 major firmware revision number */
772
773#define PKA_SW_REV_MAJOR_FW_REVISION_S 24
774#define PKA_SW_REV_MINOR_FW_REVISION_M \
775 0x00F00000 /**< 4-bit binary encoding of the
776 minor firmware revision number */
777
778#define PKA_SW_REV_MINOR_FW_REVISION_S 20
779#define PKA_SW_REV_FW_PATCH_LEVEL_M \
780 0x000F0000 /**< 4-bit binary encoding of the
781 firmware patch level, initial
782 release will carry value zero
783 Patches are used to remove bugs
784 without changing the
785 functionality or interface of a
786 module. */
787
788#define PKA_SW_REV_FW_PATCH_LEVEL_S 16
789/** @} */
790/*---------------------------------------------------------------------------*/
791/** \name PKA_REVISION register registers bit fields
792 * @{
793 */
794#define PKA_REVISION_MAJOR_HW_REVISION_M \
795 0x0F000000 /**< 4-bit binary encoding of the
796 major hardware revision number */
797
798#define PKA_REVISION_MAJOR_HW_REVISION_S 24
799#define PKA_REVISION_MINOR_HW_REVISION_M \
800 0x00F00000 /**< 4-bit binary encoding of the
801 minor hardware revision number */
802
803#define PKA_REVISION_MINOR_HW_REVISION_S 20
804#define PKA_REVISION_HW_PATCH_LEVEL_M \
805 0x000F0000 /**< 4-bit binary encoding of the
806 hardware patch level, initial
807 release will carry value zero
808 Patches are used to remove bugs
809 without changing the
810 functionality or interface of a
811 module. */
812
813#define PKA_REVISION_HW_PATCH_LEVEL_S 16
814#define PKA_REVISION_COMPLEMENT_OF_BASIC_EIP_NUMBER_M \
815 0x0000FF00 /**< Bit-by-bit logic complement of
816 bits [7:0], EIP-28 gives 0xE3 */
817
818#define PKA_REVISION_COMPLEMENT_OF_BASIC_EIP_NUMBER_S 8
819#define PKA_REVISION_BASIC_EIP_NUMBER_M \
820 0x000000FF /**< 8-bit binary encoding of the
821 EIP number, EIP-28 gives 0x1C */
822
823#define PKA_REVISION_BASIC_EIP_NUMBER_S 0
824
825/** @} */
826/*---------------------------------------------------------------------------*/
827/** \name PKA driver return codes
828 * @{
829 */
830#define PKA_STATUS_SUCCESS 0 /**< Success */
831#define PKA_STATUS_FAILURE 1 /**< Failure */
832#define PKA_STATUS_INVALID_PARAM 2 /**< Invalid parameter */
833#define PKA_STATUS_BUF_UNDERFLOW 3 /**< Buffer underflow */
834#define PKA_STATUS_RESULT_0 4 /**< Result is all zeros */
835#define PKA_STATUS_A_GR_B 5 /**< Big number compare return status if
836 the first big num is greater than
837 the second. */
838#define PKA_STATUS_A_LT_B 6 /**< Big number compare return status if
839 the first big num is less than the
840 second. */
841#define PKA_STATUS_OPERATION_INPRG 7 /**< PKA operation is in progress. */
842#define PKA_STATUS_OPERATION_NOT_INPRG 8 /**< No PKA operation is in progress. */
843#define PKA_STATUS_SIGNATURE_INVALID 9 /**< Signature is invalid. */
844#define PKA_STATUS_A_EQ_B 10
845#define PKA_STATUS_POINT_AT_INFINITY 11
846/** @} */
847/*---------------------------------------------------------------------------*/
848/** \name Required scratchpad space.
849 * @{
850 */
851#define PKA_NEXT_OFFSET(offset, words) \
852 (offset + ((words & 7) ? 8 /* ensure 64-bit boundary */ : 0) + (words & ~7))
853/** Table 22-4 */
854#define PKA_MULTIPLY_SCRATCHPAD_WORDS(alen, blen) \
855 (alen + blen + 6)
856#define PKA_ADD_SCRATCHPAD_WORDS(alen, blen) \
857 (MAX(alen, blen) + 1)
858#define PKA_SUBTRACT_SCRATCHPAD_WORDS(alen, blen) \
859 (MAX(alen, blen))
860#define PKA_LSHIFT_WORDS(len) \
861 (len + 1)
862#define PKA_DIVIDE_SCRATCHPAD_WORDS(blen) \
863 (blen + 1)
864#define PKA_QUOTIENT_WORDS(alen, blen) \
865 (alen - blen + 1)
866#define PKA_REMAINDER_WORDS(blen) \
867 (blen + 1)
868/** Table 22-16 */
869#define PKA_MOD_INV_SCRATCHPAD_WORDS(alen, blen) \
870 (5 * PKA_COORDINATE_WORDS(MAX(alen, blen)))
871/** Table 22-21 */
872#define PKA_COORDINATE_WORDS(len) \
873 (len + 2 + (len % 2))
874#define PKA_ECC_ADD_SCRATCHPAD_WORDS(blen) \
875 (2 * PKA_COORDINATE_WORDS(blen) + 5 * PKA_COORDINATE_WORDS(blen + 1))
876#define PKA_ECC_MUL_SCRATCHPAD_WORDS(blen) \
877 (18 * PKA_COORDINATE_WORDS(blen) + MAX(8, PKA_COORDINATE_WORDS(blen)))
878#define PKA_POINT_WORDS(len) \
879 (2 * PKA_COORDINATE_WORDS(len))
880/** @} */
881/*---------------------------------------------------------------------------*/
882/** \name PKA functions
883 * @{
884 */
885
886/** \brief Enables and resets the PKA engine
887 */
888void pka_init(void);
889
890/** \brief Enables the PKA engine
891 */
892void pka_enable(void);
893
894/** \brief Disables the PKA engine
895 * \note Call this function to save power when the engine is unused.
896 */
897void pka_disable(void);
898
899/** \brief Checks the status of the PKA engine operation
900 * \retval false Result not yet available, and no error occurred
901 * \retval true Result available, or error occurred
902 */
903bool pka_check_status(void);
904
905/** \brief Registers a process to be notified of the completion of a PKA
906 * operation
907 * \param p Process to be polled upon IRQ
908 * \note This function is only supposed to be called by the PKA drivers.
909 */
910void pka_register_process_notification(struct process *p);
911
912/**
913 * \brief Initiates the given PKA function.
914 */
915void pka_run_function(uint32_t pka_function);
916
917/**
918 * \brief Copies a little-endian sequence of words to the PKA RAM.
919 * \param words The lowest memory address holds the least significant word.
920 * \param num_words The number of to-be-copied words.
921 * \param offset Offset into the PKA RAM from PKA_RAM_BASE.
922 */
923void pka_little_endian_to_pka_ram(const uint32_t *words,
924 size_t num_words,
925 uintptr_t offset);
926
927/**
928 * \brief Copies a word to the PKA RAM.
929 * \param word The to-be-copied word.
930 * \param offset Offset into the PKA RAM from PKA_RAM_BASE.
931 */
932void pka_word_to_pka_ram(uint32_t word, uintptr_t offset);
933
934/**
935 * \brief Retrieves a word from the PKA RAM.
936 * \param offset Offset into the PKA RAM from PKA_RAM_BASE.
937 * \return The read word.
938 */
939uint32_t pka_word_from_pka_ram(uintptr_t offset);
940
941/**
942 * \brief Copies a big-endian sequence of bytes to the PKA RAM.
943 * \param bytes The to-be-copied bytes.
944 * \param num_bytes The number of to-be-copied bytes.
945 * \param offset Offset into the PKA RAM from PKA_RAM_BASE.
946 */
947void pka_big_endian_to_pka_ram(const uint8_t *bytes,
948 size_t num_bytes,
949 uintptr_t offset);
950
951/**
952 * \brief Retrieves a big-endian sequence of bytes from the PKA RAM.
953 * \param bytes Target location for the big-endian sequence of bytes.
954 * \param num_words The number of to-be-retrieved words.
955 * \param offset Offset into the PKA RAM from PKA_RAM_BASE.
956 */
957void pka_big_endian_from_pka_ram(uint8_t *bytes,
958 size_t num_words,
959 uintptr_t offset);
960
961/** @} */
962
963#endif /* PKA_H_ */
964
965/**
966 * @}
967 * @}
968 */
pka_word_from_pka_ram
uint32_t pka_word_from_pka_ram(uintptr_t offset)
Retrieves a word from the PKA RAM.
Definition pka.c:145
pka_run_function
void pka_run_function(uint32_t function)
Initiates the given PKA function.
Definition pka.c:116
pka_word_to_pka_ram
void pka_word_to_pka_ram(uint32_t word, uintptr_t offset)
Copies a word to the PKA RAM.
Definition pka.c:137
pka_register_process_notification
void pka_register_process_notification(struct process *p)
Registers a process to be notified of the completion of a PKA operation.
Definition pka.c:110
pka_big_endian_from_pka_ram
void pka_big_endian_from_pka_ram(uint8_t *bytes, size_t num_words, uintptr_t offset)
Retrieves a big-endian sequence of bytes from the PKA RAM.
Definition pka.c:170
pka_disable
void pka_disable(void)
Disables the PKA engine.
Definition pka.c:95
pka_init
void pka_init(void)
Enables and resets the PKA engine.
Definition pka.c:80
pka_enable
void pka_enable(void)
Enables the PKA engine.
Definition pka.c:86
pka_little_endian_to_pka_ram
void pka_little_endian_to_pka_ram(const uint32_t *words, size_t num_words, uintptr_t offset)
Copies a little-endian sequence of words to the PKA RAM.
Definition pka.c:125
pka_big_endian_to_pka_ram
void pka_big_endian_to_pka_ram(const uint8_t *bytes, size_t num_bytes, uintptr_t offset)
Copies a big-endian sequence of bytes to the PKA RAM.
Definition pka.c:153
pka_check_status
bool pka_check_status(void)
Checks the status of the PKA engine operation.
Definition pka.c:104