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Contiki-NG
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Contiki-NG
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Files | |
| file | cc2538-ecc.c |
| Implementation of PKA-accelerated ECDH and ECDSA. | |
| file | pka.c |
| Implementation of the cc2538 PKA engine driver. | |
| file | pka.h |
| Header file for the cc2538 PKA engine driver. | |
Functions | |
| static bool | test_bit (const uint32_t *element, size_t bit) |
| Tells if a bit in a little-endian element is set. | |
| void | pka_isr (void) |
| The PKA engine ISR. | |
PKA functions | |
| void | pka_init (void) |
| Enables and resets the PKA engine. | |
| void | pka_enable (void) |
| Enables the PKA engine. | |
| void | pka_disable (void) |
| Disables the PKA engine. | |
| bool | pka_check_status (void) |
| Checks the status of the PKA engine operation. | |
| void | pka_register_process_notification (struct process *p) |
| Registers a process to be notified of the completion of a PKA operation. | |
| void | pka_run_function (uint32_t pka_function) |
| Initiates the given PKA function. | |
| void | pka_little_endian_to_pka_ram (const uint32_t *words, size_t num_words, uintptr_t offset) |
| Copies a little-endian sequence of words to the PKA RAM. | |
| void | pka_word_to_pka_ram (uint32_t word, uintptr_t offset) |
| Copies a word to the PKA RAM. | |
| uint32_t | pka_word_from_pka_ram (uintptr_t offset) |
| Retrieves a word from the PKA RAM. | |
| void | pka_big_endian_to_pka_ram (const uint8_t *bytes, size_t num_bytes, uintptr_t offset) |
| Copies a big-endian sequence of bytes to the PKA RAM. | |
| void | pka_big_endian_from_pka_ram (uint8_t *bytes, size_t num_words, uintptr_t offset) |
| Retrieves a big-endian sequence of bytes from the PKA RAM. | |
PKA register offsets | |
| #define | PKA_APTR 0x44004000 |
| PKA vector A address During execution of basic PKCP operations, this register is double buffered and can be written with a new value for the next operation; when not written, the value remains intact. | |
| #define | PKA_BPTR 0x44004004 |
| PKA vector B address During execution of basic PKCP operations, this register is double buffered and can be written with a new value for the next operation; when not written, the value remains intact. | |
| #define | PKA_CPTR 0x44004008 |
| PKA vector C address During execution of basic PKCP operations, this register is double buffered and can be written with a new value for the next operation; when not written, the value remains intact. | |
| #define | PKA_DPTR 0x4400400C |
| PKA vector D address During execution of basic PKCP operations, this register is double buffered and can be written with a new value for the next operation; when not written, the value remains intact. | |
| #define | PKA_ALENGTH 0x44004010 |
| PKA vector A length During execution of basic PKCP operations, this register is double buffered and can be written with a new value for the next operation; when not written, the value remains intact. | |
| #define | PKA_BLENGTH 0x44004014 |
| PKA vector B length During execution of basic PKCP operations, this register is double buffered and can be written with a new value for the next operation; when not written, the value remains intact. | |
| #define | PKA_SHIFT 0x44004018 |
| PKA bit shift value For basic PKCP operations, modifying the contents of this register is made impossible while the operation is being performed. | |
| #define | PKA_FUNCTION 0x4400401C |
| PKA function This register contains the control bits to start basic PKCP as well as complex sequencer operations. | |
| #define | PKA_COMPARE 0x44004020 |
| PKA compare result This register provides the result of a basic PKCP compare operation. | |
| #define | PKA_MSW 0x44004024 |
| PKA most-significant-word of result vector This register indicates the (word) address in the PKA RAM where the most significant nonzero 32-bit word of the result is stored. | |
| #define | PKA_DIVMSW 0x44004028 |
| PKA most-significant-word of divide remainder This register indicates the (32-bit word) address in the PKA RAM where the most significant nonzero 32-bit word of the remainder result for the basic divide and modulo operations is stored. | |
| #define | PKA_SEQ_CTRL 0x440040C8 |
| PKA sequencer control and status register The sequencer is interfaced with the outside world through a single control and status register. | |
| #define | PKA_OPTIONS 0x440040F4 |
| PKA hardware options register This register provides the host with a means to determine the hardware configuration implemented in this PKA engine, focused on options that have an effect on software interacting with the module. | |
| #define | PKA_SW_REV 0x440040F8 |
| PKA firmware revision and capabilities register This register allows the host access to the internal firmware revision number of the PKA Engine for software driver matching and diagnostic purposes. | |
| #define | PKA_REVISION 0x440040FC |
| PKA hardware revision register This register allows the host access to the hardware revision number of the PKA engine for software driver matching and diagnostic purposes. | |
PKA_APTR register registers bit fields | |
| #define | PKA_APTR_APTR_M 0x000007FF |
| This register specifies the location of vector A within the PKA RAM. | |
PKA_BPTR register registers bit fields | |
| #define | PKA_BPTR_BPTR_M 0x000007FF |
| This register specifies the location of vector B within the PKA RAM. | |
PKA_CPTR register registers bit fields | |
| #define | PKA_CPTR_CPTR_M 0x000007FF |
| This register specifies the location of vector C within the PKA RAM. | |
PKA_DPTR register registers bit fields | |
| #define | PKA_DPTR_DPTR_M 0x000007FF |
| This register specifies the location of vector D within the PKA RAM. | |
PKA_ALENGTH register registers bit fields | |
| #define | PKA_ALENGTH_ALENGTH_M 0x000001FF |
| This register specifies the length (in 32-bit words) of Vector A. | |
PKA_BLENGTH register registers bit fields | |
| #define | PKA_BLENGTH_BLENGTH_M 0x000001FF |
| This register specifies the length (in 32-bit words) of Vector B. | |
PKA_FUNCTION register registers bit fields | |
| #define | PKA_FUNCTION_STALL_RESULT 0x01000000 |
| When written with a 1b, updating of the PKA_COMPARE, PKA_MSW and PKA_DIVMSW registers, as well as resetting the run bit is stalled beyond the point that a running operation is actually finished. | |
| #define | PKA_FUNCTION_RUN 0x00008000 |
| The host sets this bit to instruct the PKA module to begin processing the basic PKCP or complex sequencer operation. | |
| #define | PKA_FUNCTION_SEQUENCER_OPERATIONS_M 0x00007000 |
| These bits select the complex sequencer operation to perform: 000b: None 001b: ExpMod-CRT 010b: ExpMod-ACT4 (compatible with EIP2315) 011b: ECC-ADD (if available in firmware, otherwise reserved) 100b: ExpMod-ACT2 (compatible with EIP2316) 101b: ECC-MUL (if available in firmware, otherwise reserved) 110b: ExpMod-variable 111b: ModInv (if available in firmware, otherwise reserved) The encoding of these operations is determined by sequencer firmware. | |
| #define | PKA_FUNCTION_COPY 0x00000800 |
| Perform copy operation. | |
| #define | PKA_FUNCTION_COMPARE 0x00000400 |
| Perform compare operation. | |
| #define | PKA_FUNCTION_MODULO 0x00000200 |
| Perform modulo operation. | |
| #define | PKA_FUNCTION_DIVIDE 0x00000100 |
| Perform divide operation. | |
| #define | PKA_FUNCTION_LSHIFT 0x00000080 |
| Perform left shift operation. | |
| #define | PKA_FUNCTION_RSHIFT 0x00000040 |
| Perform right shift operation. | |
| #define | PKA_FUNCTION_SUBTRACT 0x00000020 |
| Perform subtract operation. | |
| #define | PKA_FUNCTION_ADD 0x00000010 |
| Perform add operation. | |
| #define | PKA_FUNCTION_MS_ONE 0x00000008 |
| Loads the location of the Most Significant one bit within the result word indicated in the PKA_MSW register into bits [4:0] of the PKA_DIVMSW register - can only be used with basic PKCP operations, except for Divide, Modulo and Compare. | |
| #define | PKA_FUNCTION_ADDSUB 0x00000002 |
| Perform combined add/subtract operation. | |
| #define | PKA_FUNCTION_MULTIPLY 0x00000001 |
| Perform multiply operation. | |
PKA_SEQ_CTRL register registers bit fields | |
| #define | PKA_SEQ_CTRL_RESET 0x80000000 |
| Option program ROM: Reset value = 0. | |
| #define | PKA_SEQ_CTRL_SEQUENCER_STATUS_M 0x0000FF00 |
| These read-only bits can be used by the sequencer to communicate status to the outside world. | |
| #define | PKA_SEQ_CTRL_SW_CONTROL_STATUS_M 0x000000FF |
| These bits can be used by software to trigger sequencer operations. | |
PKA_OPTIONS register registers bit fields | |
| #define | PKA_OPTIONS_FIRST_LNME_FIFO_DEPTH_M 0xFF000000 |
| Number of words in the first LNME's FIFO RAM Should be ignored if LNME configuration is 0. | |
| #define | PKA_OPTIONS_FIRST_LNME_NR_OF_PES_M 0x003F0000 |
| Number of processing elements in the pipeline of the first LNME Should be ignored if LNME configuration is 0. | |
| #define | PKA_OPTIONS_MMM3A 0x00001000 |
| Reserved for a future functional extension to the LNME Always 0b. | |
| #define | PKA_OPTIONS_INT_MASKING 0x00000800 |
| Value 0b indicates that the main interrupt output (bit [1] of the interrupts output bus) is the direct complement of the run bit in the PKA_CONTROL register, value 1b indicates that interrupt masking logic is present for this output. | |
| #define | PKA_OPTIONS_PROTECTION_OPTION_M 0x00000700 |
| Value 0 indicates no additional protection against side channel attacks, value 1 indicates the SCAP option, value 3 indicates the PROT option; other values are reserved. | |
| #define | PKA_OPTIONS_PROGRAM_RAM 0x00000080 |
| Value 1b indicates sequencer program storage in RAM, value 0b in ROM. | |
| #define | PKA_OPTIONS_SEQUENCER_CONFIGURATION_M 0x00000060 |
| Value 1 indicates a standard sequencer; other values are reserved. | |
| #define | PKA_OPTIONS_LNME_CONFIGURATION_M 0x0000001C |
| Value 0 indicates NO LNME, value 1 indicates one standard LNME (with alpha = 32, beta = 8); other values reserved. | |
| #define | PKA_OPTIONS_PKCP_CONFIGURATION_M 0x00000003 |
| Value 1 indicates a PKCP with a 16x16 multiplier, value 2 indicates a PKCP with a 32x32 multiplier, other values reserved. | |
PKA_SW_REV register registers bit fields | |
| #define | PKA_SW_REV_FW_CAPABILITIES_M 0xF0000000 |
| 4-bit binary encoding for the functionality implemented in the firmware. | |
| #define | PKA_SW_REV_MAJOR_FW_REVISION_M 0x0F000000 |
| 4-bit binary encoding of the major firmware revision number | |
| #define | PKA_SW_REV_MINOR_FW_REVISION_M 0x00F00000 |
| 4-bit binary encoding of the minor firmware revision number | |
| #define | PKA_SW_REV_FW_PATCH_LEVEL_M 0x000F0000 |
| 4-bit binary encoding of the firmware patch level, initial release will carry value zero Patches are used to remove bugs without changing the functionality or interface of a module. | |
Required scratchpad space. | |
| #define | PKA_MULTIPLY_SCRATCHPAD_WORDS(alen, blen) (alen + blen + 6) |
| Table 22-4. | |
| #define | PKA_MOD_INV_SCRATCHPAD_WORDS(alen, blen) (5 * PKA_COORDINATE_WORDS(MAX(alen, blen))) |
| Table 22-16. | |
| #define | PKA_COORDINATE_WORDS(len) (len + 2 + (len % 2)) |
| Table 22-21. | |
Driver for the cc2538 PKA engine
| #define PKA_ALENGTH 0x44004010 |
PKA vector A length During execution of basic PKCP operations, this register is double buffered and can be written with a new value for the next operation; when not written, the value remains intact.
During the execution of sequencer-controlled complex operations, this register may not be written and its value is undefined at the conclusion of the operation. The driver software cannot rely on the written value to remain intact.
| #define PKA_APTR 0x44004000 |
PKA vector A address During execution of basic PKCP operations, this register is double buffered and can be written with a new value for the next operation; when not written, the value remains intact.
During the execution of sequencer-controlled complex operations, this register may not be written and its value is undefined at the conclusion of the operation. The driver software cannot rely on the written value to remain intact.
| #define PKA_APTR_APTR_M 0x000007FF |
| #define PKA_BLENGTH 0x44004014 |
PKA vector B length During execution of basic PKCP operations, this register is double buffered and can be written with a new value for the next operation; when not written, the value remains intact.
During the execution of sequencer-controlled complex operations, this register may not be written and its value is undefined at the conclusion of the operation. The driver software cannot rely on the written value to remain intact.
| #define PKA_BPTR 0x44004004 |
PKA vector B address During execution of basic PKCP operations, this register is double buffered and can be written with a new value for the next operation; when not written, the value remains intact.
During the execution of sequencer-controlled complex operations, this register may not be written and its value is undefined at the conclusion of the operation. The driver software cannot rely on the written value to remain intact.
| #define PKA_BPTR_BPTR_M 0x000007FF |
| #define PKA_COMPARE 0x44004020 |
| #define PKA_CPTR 0x44004008 |
PKA vector C address During execution of basic PKCP operations, this register is double buffered and can be written with a new value for the next operation; when not written, the value remains intact.
During the execution of sequencer-controlled complex operations, this register may not be written and its value is undefined at the conclusion of the operation. The driver software cannot rely on the written value to remain intact.
| #define PKA_CPTR_CPTR_M 0x000007FF |
| #define PKA_DIVMSW 0x44004028 |
PKA most-significant-word of divide remainder This register indicates the (32-bit word) address in the PKA RAM where the most significant nonzero 32-bit word of the remainder result for the basic divide and modulo operations is stored.
Bits [4:0] are loaded with the bit number of the most-significant nonzero bit in the most-significant nonzero word when MS one control bit is set. For divide, modulo, and MS one reporting, this register is updated when the RUN bit in the PKA_FUNCTION register is reset at the end of the operation. For the complex sequencer controlled operations, updating of bits [4:0] of this register with the most-significant bit location of the actual result is done near the end of the operation. The result is meaningful only if no errors were detected and that for ECC operations; the PKA_DIVMSW register provides information for the x-coordinate of the result point only.
| #define PKA_DPTR 0x4400400C |
PKA vector D address During execution of basic PKCP operations, this register is double buffered and can be written with a new value for the next operation; when not written, the value remains intact.
During the execution of sequencer-controlled complex operations, this register may not be written and its value is undefined at the conclusion of the operation. The driver software cannot rely on the written value to remain intact.
| #define PKA_DPTR_DPTR_M 0x000007FF |
| #define PKA_FUNCTION 0x4400401C |
PKA function This register contains the control bits to start basic PKCP as well as complex sequencer operations.
The run bit can be used to poll for the completion of the operation. Modifying bits [11:0] is made impossible during the execution of a basic PKCP operation. During the execution of sequencer-controlled complex operations, this register is modified; the run and stall result bits are set to zero at the conclusion, but other bits are undefined. Attention: Continuously reading this register to poll the run bit is not allowed when executing complex sequencer operations (the sequencer cannot access the PKCP when this is done). Leave at least one sysclk cycle between poll operations.
Definition at line 174 of file pka.h.
Referenced by pka_check_status(), and pka_run_function().
| #define PKA_FUNCTION_RUN 0x00008000 |
The host sets this bit to instruct the PKA module to begin processing the basic PKCP or complex sequencer operation.
This bit is reset low automatically when the operation is complete. The complement of this bit is output as interrupts[1]. After a reset, the run bit is always set to 1b. Depending on the option, program ROM or program RAM, the following applies: Program ROM - The first sequencer instruction sets the bit to 0b. This is done immediately after the hardware reset is released. Program RAM - The sequencer must set the bit to 0b. As a valid firmware may not have been loaded, the sequencer is held in software reset after the hardware reset is released (the reset bit in PKA_SEQ_CRTL is set to 1b). After the FW image is loaded and the Reset bit is cleared, the sequencer starts to execute the FW. The first instruction clears the run bit. In both cases a few clock cycles are needed before the first instruction is executed and the run bit state has been propagated.
Definition at line 439 of file pka.h.
Referenced by pka_check_status(), and pka_run_function().
| #define PKA_FUNCTION_STALL_RESULT 0x01000000 |
When written with a 1b, updating of the PKA_COMPARE, PKA_MSW and PKA_DIVMSW registers, as well as resetting the run bit is stalled beyond the point that a running operation is actually finished.
Use this to allow software enough time to read results from a previous operation when the newly started operation is known to take only a short amount of time. If a result is waiting, the result registers is updated and the run bit is reset in the clock cycle following writing the stall result bit back to 0b. The Stall result function may only be used for basic PKCP operations.
| #define PKA_MSW 0x44004024 |
PKA most-significant-word of result vector This register indicates the (word) address in the PKA RAM where the most significant nonzero 32-bit word of the result is stored.
Should be ignored for modulo operations. For basic PKCP operations, this register is updated when the run bit in the PKA_FUNCTION register is reset at the end of the operation. For the complex-sequencer controlled operations, updating of the final value matching the actual result is done near the end of the operation; note that the result is only meaningful if no errors were detected and that for ECC operations, the PKA_MSW register will provide information for the x-coordinate of the result point only.
| #define PKA_OPTIONS 0x440040F4 |
PKA hardware options register This register provides the host with a means to determine the hardware configuration implemented in this PKA engine, focused on options that have an effect on software interacting with the module.
Note: (32 x (1st LNME nr. of PEs + 1st LNME FIFO RAM depth - 10)) equals the maximum modulus vector length (in bits) that can be handled by the modular exponentiation and ECC operations executed on a PKA engine that includes an LNME.
| #define PKA_OPTIONS_FIRST_LNME_FIFO_DEPTH_M 0xFF000000 |
| #define PKA_OPTIONS_FIRST_LNME_NR_OF_PES_M 0x003F0000 |
| #define PKA_OPTIONS_INT_MASKING 0x00000800 |
Value 0b indicates that the main interrupt output (bit [1] of the interrupts output bus) is the direct complement of the run bit in the PKA_CONTROL register, value 1b indicates that interrupt masking logic is present for this output.
Note: Reset value is undefined
| #define PKA_OPTIONS_LNME_CONFIGURATION_M 0x0000001C |
| #define PKA_OPTIONS_PKCP_CONFIGURATION_M 0x00000003 |
| #define PKA_OPTIONS_PROGRAM_RAM 0x00000080 |
| #define PKA_OPTIONS_PROTECTION_OPTION_M 0x00000700 |
| #define PKA_REVISION 0x440040FC |
PKA hardware revision register This register allows the host access to the hardware revision number of the PKA engine for software driver matching and diagnostic purposes.
It is always located at the highest address in the access space of the module and contains an encoding of the EIP number (with its complement as signature) for recognition of the hardware module.
| #define PKA_SEQ_CTRL 0x440040C8 |
PKA sequencer control and status register The sequencer is interfaced with the outside world through a single control and status register.
With the exception of bit [31], the actual use of bits in the separate sub-fields of this register is determined by the sequencer firmware. This register need only be accessed when the sequencer program is stored in RAM. The reset value of the RESTE bit depends upon the option chosen for sequencer program storage.
| #define PKA_SEQ_CTRL_RESET 0x80000000 |
Option program ROM: Reset value = 0.
Read/Write, reset value 0b (ZERO). Writing 1b resets the sequencer, write to 0b to restart operations again. As the reset value is 0b, the sequencer will automatically start operations executing from program ROM. This bit should always be written with zero and ignored when reading this register. Option Program RAM: Reset value =1. Read/Write, reset value 1b (ONE). When 1b, the sequencer is held in a reset state and the PKA_PROGRAM area is accessible for loading the sequencer program (while the PKA_DATA_RAM is inaccessible), write to 0b to (re)start sequencer operations and disable PKA_PROGRAM area accessibility (also enables the PKA_DATA_RAM accesses). Resetting the sequencer (in order to load other firmware) should only be done when the PKA Engine is not performing any operations (i.e. the run bit in the PKA_FUNCTION register should be zero).
| #define PKA_SEQ_CTRL_SEQUENCER_STATUS_M 0x0000FF00 |
These read-only bits can be used by the sequencer to communicate status to the outside world.
Bit [8] is also used as sequencer interrupt, with the complement of this bit ORed into the run bit in PKA_FUNCTION. This field should always be written with zeroes and ignored when reading this register.
| #define PKA_SEQ_CTRL_SW_CONTROL_STATUS_M 0x000000FF |
These bits can be used by software to trigger sequencer operations.
External logic can set these bits by writing 1b, cannot reset them by writing 0b. The sequencer can reset these bits by writing 0b, cannot set them by writing 1b. Setting the run bit in PKA_FUNCTION together with a nonzero sequencer operations field automatically sets bit [0] here. This field should always be written with zeroes and ignored when reading this register.
| #define PKA_SHIFT 0x44004018 |
PKA bit shift value For basic PKCP operations, modifying the contents of this register is made impossible while the operation is being performed.
For the ExpMod-variable and ExpMod-CRT operations, this register is used to indicate the number of odd powers to use (directly as a value in the range 1-16). For the ModInv and ECC operations, this register is used to hold a completion code.
| #define PKA_SW_REV 0x440040F8 |
PKA firmware revision and capabilities register This register allows the host access to the internal firmware revision number of the PKA Engine for software driver matching and diagnostic purposes.
This register also contains a field that encodes the capabilities of the embedded firmware. The PKA_SW_REV register is written by the firmware within a few clock cycles after starting up that firmware. The hardware reset value is zero, indicating that the information has not been written yet.
| #define PKA_SW_REV_FW_CAPABILITIES_M 0xF0000000 |
| void pka_big_endian_from_pka_ram | ( | uint8_t * | bytes, |
| size_t | num_words, | ||
| uintptr_t | offset ) |
Retrieves a big-endian sequence of bytes from the PKA RAM.
| bytes | Target location for the big-endian sequence of bytes. |
| num_words | The number of to-be-retrieved words. |
| offset | Offset into the PKA RAM from PKA_RAM_BASE. |
Definition at line 170 of file pka.c.
References PKA_RAM_BASE.
| void pka_big_endian_to_pka_ram | ( | const uint8_t * | bytes, |
| size_t | num_bytes, | ||
| uintptr_t | offset ) |
Copies a big-endian sequence of bytes to the PKA RAM.
| bytes | The to-be-copied bytes. |
| num_bytes | The number of to-be-copied bytes. |
| offset | Offset into the PKA RAM from PKA_RAM_BASE. |
Definition at line 153 of file pka.c.
References PKA_RAM_BASE.
| bool pka_check_status | ( | void | ) |
Checks the status of the PKA engine operation.
| false | Result not yet available, and no error occurred |
| true | Result available, or error occurred |
Definition at line 104 of file pka.c.
References PKA_FUNCTION, and PKA_FUNCTION_RUN.
| void pka_disable | ( | void | ) |
Disables the PKA engine.
Definition at line 95 of file pka.c.
References SYS_CTRL_DCGCSEC, SYS_CTRL_RCGCSEC, and SYS_CTRL_SCGCSEC.
| void pka_isr | ( | void | ) |
The PKA engine ISR.
This is the interrupt service routine for the PKA engine. This ISR is called at worst from PM0, so lpm_exit() does not need to be called.
Definition at line 62 of file pka.c.
References PKA_IRQn, and process_poll().
| void pka_little_endian_to_pka_ram | ( | const uint32_t * | words, |
| size_t | num_words, | ||
| uintptr_t | offset ) |
Copies a little-endian sequence of words to the PKA RAM.
| words | The lowest memory address holds the least significant word. |
| num_words | The number of to-be-copied words. |
| offset | Offset into the PKA RAM from PKA_RAM_BASE. |
Definition at line 125 of file pka.c.
References PKA_RAM_BASE.
| void pka_register_process_notification | ( | struct process * | p | ) |
Registers a process to be notified of the completion of a PKA operation.
| p | Process to be polled upon IRQ |
Definition at line 110 of file pka.c.
Referenced by pka_run_function().
| uint32_t pka_word_from_pka_ram | ( | uintptr_t | offset | ) |
Retrieves a word from the PKA RAM.
| offset | Offset into the PKA RAM from PKA_RAM_BASE. |
Definition at line 145 of file pka.c.
References PKA_RAM_BASE.
| void pka_word_to_pka_ram | ( | uint32_t | word, |
| uintptr_t | offset ) |
Copies a word to the PKA RAM.
| word | The to-be-copied word. |
| offset | Offset into the PKA RAM from PKA_RAM_BASE. |
Definition at line 137 of file pka.c.
References PKA_RAM_BASE.
|
static |
Tells if a bit in a little-endian element is set.
| element | Little-endian element. |
| bit | Index of the bit; the least significant bit has index 0. |
Definition at line 105 of file cc2538-ecc.c.
1.10.0