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50 #define RADIO_PHY_OVERHEAD 3
52 #define RADIO_BYTE_AIR_TIME 32
55#define RADIO_DELAY_BEFORE_TX ((unsigned)US_TO_RTIMERTICKS(456))
58#define RADIO_DELAY_BEFORE_RX ((unsigned)US_TO_RTIMERTICKS(183))
60#define RADIO_DELAY_BEFORE_DETECT 0
62#define PLATFORM_HAS_LEDS 1
63#define PLATFORM_HAS_BUTTON 1
64#define PLATFORM_HAS_RADIO 1
65#define PLATFORM_HAS_BATTERY 1
68#define F_CPU 8000000uL
71#define NETSTACK_CONF_RADIO cc2420_driver
74#ifdef __IAR_SYSTEMS_ICC__
76#define P1SEL2_ (0x0041u)
80#define P5SEL2_ (0x0045u)
103#define LEDS_PxDIR P4DIR
104#define LEDS_PxOUT P4OUT
105#define LEDS_CONF_RED 0x04
106#define LEDS_CONF_GREEN 0x01
107#define LEDS_CONF_YELLOW 0x80
109#define LEDS_PxDIR P5DIR
110#define LEDS_PxOUT P5OUT
111#define LEDS_CONF_RED 0x10
112#define LEDS_CONF_GREEN 0x40
113#define LEDS_CONF_YELLOW 0x20
116#define LEDS_CONF_LEGACY_API 1
119#ifndef DCOSYNCH_CONF_ENABLED
120#define DCOSYNCH_CONF_ENABLED (!(MAC_CONF_WITH_TSCH))
124#ifndef CC2420_CONF_SFD_TIMESTAMPS
125#define CC2420_CONF_SFD_TIMESTAMPS (MAC_CONF_WITH_TSCH)
128#ifndef DCOSYNCH_CONF_PERIOD
129#define DCOSYNCH_CONF_PERIOD 30
132#define ROM_ERASE_UNIT_SIZE 512
133#define XMEM_ERASE_UNIT_SIZE (64 * 1024L)
135#define CFS_CONF_OFFSET_TYPE long
138#define NODE_ID_XMEM_OFFSET (0 * XMEM_ERASE_UNIT_SIZE)
141#define EEPROMFS_ADDR_CODEPROP (1 * XMEM_ERASE_UNIT_SIZE)
143#define CFS_XMEM_CONF_OFFSET (2 * XMEM_ERASE_UNIT_SIZE)
144#define CFS_XMEM_CONF_SIZE (1 * XMEM_ERASE_UNIT_SIZE)
146#define CFS_RAM_CONF_SIZE 4096
153#define SPI_TXBUF UCB0TXBUF
154#define SPI_RXBUF UCB0RXBUF
157#define SPI_WAITFOREOTx() while((UCB0STAT & UCBUSY) != 0)
159#define SPI_WAITFOREORx() while((IFG2 & UCB0RXIFG) == 0)
161#define SPI_WAITFORTxREADY() while((IFG2 & UCB0TXIFG) == 0)
176#define SPI_FLASH_ENABLE() (P4OUT &= ~BV(FLASH_CS))
177#define SPI_FLASH_DISABLE() (P4OUT |= BV(FLASH_CS))
179#define SPI_FLASH_HOLD() (P5OUT &= ~BV(FLASH_HOLD))
180#define SPI_FLASH_UNHOLD() (P5OUT |= BV(FLASH_HOLD))
186#define CC2420_CONF_SYMBOL_LOOP_COUNT 1302
189#define CC2420_FIFOP_PORT(type) P1##type
190#define CC2420_FIFOP_PIN 2
192#define CC2420_FIFO_PORT(type) P1##type
193#define CC2420_FIFO_PIN 3
195#define CC2420_CCA_PORT(type) P1##type
196#define CC2420_CCA_PIN 4
198#define CC2420_SFD_PORT(type) P4##type
199#define CC2420_SFD_PIN 1
201#define CC2420_CSN_PORT(type) P3##type
202#define CC2420_CSN_PIN 0
204#define CC2420_VREG_PORT(type) P4##type
205#define CC2420_VREG_PIN 5
207#define CC2420_RESET_PORT(type) P4##type
208#define CC2420_RESET_PIN 6
210#define CC2420_IRQ_VECTOR PORT1_VECTOR
213#define CC2420_FIFOP_IS_1 (!!(CC2420_FIFOP_PORT(IN) & BV(CC2420_FIFOP_PIN)))
214#define CC2420_FIFO_IS_1 (!!(CC2420_FIFO_PORT(IN) & BV(CC2420_FIFO_PIN)))
215#define CC2420_CCA_IS_1 (!!(CC2420_CCA_PORT(IN) & BV(CC2420_CCA_PIN)))
216#define CC2420_SFD_IS_1 (!!(CC2420_SFD_PORT(IN) & BV(CC2420_SFD_PIN)))
219#define SET_RESET_INACTIVE() (CC2420_RESET_PORT(OUT) |= BV(CC2420_RESET_PIN))
220#define SET_RESET_ACTIVE() (CC2420_RESET_PORT(OUT) &= ~BV(CC2420_RESET_PIN))
223#define SET_VREG_ACTIVE() (CC2420_VREG_PORT(OUT) |= BV(CC2420_VREG_PIN))
224#define SET_VREG_INACTIVE() (CC2420_VREG_PORT(OUT) &= ~BV(CC2420_VREG_PIN))
227#define CC2420_FIFOP_INT_INIT() do { \
228 CC2420_FIFOP_PORT(IES) &= ~BV(CC2420_FIFOP_PIN); \
229 CC2420_CLEAR_FIFOP_INT(); \
233#define CC2420_ENABLE_FIFOP_INT() do { CC2420_FIFOP_PORT(IE) |= BV(CC2420_FIFOP_PIN); } while(0)
234#define CC2420_DISABLE_FIFOP_INT() do { CC2420_FIFOP_PORT(IE) &= ~BV(CC2420_FIFOP_PIN); } while(0)
235#define CC2420_CLEAR_FIFOP_INT() do { CC2420_FIFOP_PORT(IFG) &= ~BV(CC2420_FIFOP_PIN); } while(0)
243#define CC2420_SPI_ENABLE() (CC2420_CSN_PORT(OUT) &= ~BV(CC2420_CSN_PIN))
245#define CC2420_SPI_DISABLE() (CC2420_CSN_PORT(OUT) |= BV(CC2420_CSN_PIN))
246#define CC2420_SPI_IS_ENABLED() ((CC2420_CSN_PORT(OUT) & BV(CC2420_CSN_PIN)) != BV(CC2420_CSN_PIN))
252#define I2C_PxDIR P5DIR
254#define I2C_PxOUT P5OUT
255#define I2C_PxSEL P5SEL
256#define I2C_PxSEL2 P5SEL2
257#define I2C_PxREN P5REN
259#define I2C_SDA (1 << 1)
260#define I2C_SCL (1 << 2)
261#define I2C_PRESC_1KHZ_LSB 0x00
262#define I2C_PRESC_1KHZ_MSB 0x20
263#define I2C_PRESC_100KHZ_LSB 0x50
264#define I2C_PRESC_100KHZ_MSB 0x00
265#define I2C_PRESC_400KHZ_LSB 0x14
266#define I2C_PRESC_400KHZ_MSB 0x00
269#ifndef I2C_PRESC_Z1_LSB
270#define I2C_PRESC_Z1_LSB I2C_PRESC_400KHZ_LSB
273#ifndef I2C_PRESC_Z1_MSB
274#define I2C_PRESC_Z1_MSB I2C_PRESC_400KHZ_MSB
278#ifdef I2C_CONF_RX_WITH_INTERRUPT
279#define I2C_RX_WITH_INTERRUPT I2C_CONF_RX_WITH_INTERRUPT
281#define I2C_RX_WITH_INTERRUPT 1
285#define STACK_CONF_ORIGIN ((void *)0x3100)