39#ifndef NRF_DRV_CONFIG_H
40#define NRF_DRV_CONFIG_H
43#define CLOCK_CONFIG_XTAL_FREQ NRF_CLOCK_XTALFREQ_Default
44#define CLOCK_CONFIG_LF_SRC NRF_CLOCK_LF_SRC_Xtal
45#define CLOCK_CONFIG_LF_RC_CAL_INTERVAL RC_2000MS_CALIBRATION_INTERVAL
46#define CLOCK_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
49#define GPIOTE_ENABLED 1
51#if (GPIOTE_ENABLED == 1)
52#define GPIOTE_CONFIG_USE_SWI_EGU false
53#define GPIOTE_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
54#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 4
58#define TIMER0_ENABLED 0
60#if (TIMER0_ENABLED == 1)
61#define TIMER0_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
62#define TIMER0_CONFIG_MODE TIMER_MODE_MODE_Timer
63#define TIMER0_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_32Bit
64#define TIMER0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
66#define TIMER0_INSTANCE_INDEX 0
69#define TIMER1_ENABLED 1
71#if (TIMER1_ENABLED == 1)
72#define TIMER1_CONFIG_FREQUENCY NRF_TIMER_FREQ_62500Hz
73#define TIMER1_CONFIG_MODE TIMER_MODE_MODE_Timer
74#define TIMER1_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_32Bit
75#define TIMER1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
77#define TIMER1_INSTANCE_INDEX (TIMER0_ENABLED)
80#define TIMER2_ENABLED 0
82#if (TIMER2_ENABLED == 1)
83#define TIMER2_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
84#define TIMER2_CONFIG_MODE TIMER_MODE_MODE_Timer
85#define TIMER2_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
86#define TIMER2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
88#define TIMER2_INSTANCE_INDEX (TIMER1_ENABLED+TIMER0_ENABLED)
91#define TIMER3_ENABLED 0
93#if (TIMER3_ENABLED == 1)
94#define TIMER3_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
95#define TIMER3_CONFIG_MODE TIMER_MODE_MODE_Timer
96#define TIMER3_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
97#define TIMER3_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
99#define TIMER3_INSTANCE_INDEX (TIMER2_ENABLED+TIMER2_INSTANCE_INDEX)
102#define TIMER4_ENABLED 0
104#if (TIMER4_ENABLED == 1)
105#define TIMER4_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
106#define TIMER4_CONFIG_MODE TIMER_MODE_MODE_Timer
107#define TIMER4_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
108#define TIMER4_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
110#define TIMER4_INSTANCE_INDEX (TIMER3_ENABLED+TIMER3_INSTANCE_INDEX)
114#define TIMER_COUNT (TIMER0_ENABLED + TIMER1_ENABLED + TIMER2_ENABLED + TIMER3_ENABLED + TIMER4_ENABLED)
117#define RTC0_ENABLED 0
119#if (RTC0_ENABLED == 1)
120#define RTC0_CONFIG_FREQUENCY 32678
121#define RTC0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
122#define RTC0_CONFIG_RELIABLE false
124#define RTC0_INSTANCE_INDEX 0
127#define RTC1_ENABLED 1
129#if (RTC1_ENABLED == 1)
130#define RTC1_CONFIG_FREQUENCY 128
131#define RTC1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
132#define RTC1_CONFIG_RELIABLE false
134#define RTC1_INSTANCE_INDEX (RTC0_ENABLED)
137#define RTC_COUNT (RTC0_ENABLED+RTC1_ENABLED)
139#define NRF_MAXIMUM_LATENCY_US 2000
144#if (RNG_ENABLED == 1)
145#define RNG_CONFIG_ERROR_CORRECTION true
146#define RNG_CONFIG_POOL_SIZE 8
147#define RNG_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
151#define SPI0_ENABLED 0
153#if (SPI0_ENABLED == 1)
154#define SPI0_USE_EASY_DMA 0
156#define SPI0_CONFIG_SCK_PIN 2
157#define SPI0_CONFIG_MOSI_PIN 3
158#define SPI0_CONFIG_MISO_PIN 4
159#define SPI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
161#define SPI0_INSTANCE_INDEX 0
164#define SPI1_ENABLED 0
166#if (SPI1_ENABLED == 1)
167#define SPI1_USE_EASY_DMA 0
169#define SPI1_CONFIG_SCK_PIN 2
170#define SPI1_CONFIG_MOSI_PIN 3
171#define SPI1_CONFIG_MISO_PIN 4
172#define SPI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
174#define SPI1_INSTANCE_INDEX (SPI0_ENABLED)
177#define SPI2_ENABLED 0
179#if (SPI2_ENABLED == 1)
180#define SPI2_USE_EASY_DMA 0
182#define SPI2_CONFIG_SCK_PIN 2
183#define SPI2_CONFIG_MOSI_PIN 3
184#define SPI2_CONFIG_MISO_PIN 4
185#define SPI2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
187#define SPI2_INSTANCE_INDEX (SPI0_ENABLED + SPI1_ENABLED)
190#define SPI_COUNT (SPI0_ENABLED + SPI1_ENABLED + SPI2_ENABLED)
193#define UART0_ENABLED 1
195#if (UART0_ENABLED == 1)
196#define UART0_CONFIG_HWFC NRF_UART_HWFC_DISABLED
197#define UART0_CONFIG_PARITY NRF_UART_PARITY_EXCLUDED
198#define UART0_CONFIG_BAUDRATE NRF_UART_BAUDRATE_115200
199#define UART0_CONFIG_PSEL_TXD 6
200#define UART0_CONFIG_PSEL_RXD 8
201#define UART0_CONFIG_PSEL_CTS 7
202#define UART0_CONFIG_PSEL_RTS 5
203#define UART0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
205#define UART0_CONFIG_USE_EASY_DMA false
207#define UART_EASY_DMA_SUPPORT 1
208#define UART_LEGACY_SUPPORT 1
212#define TWI0_ENABLED 0
214#if (TWI0_ENABLED == 1)
215#define TWI0_CONFIG_FREQUENCY NRF_TWI_FREQ_100K
216#define TWI0_CONFIG_SCL 0
217#define TWI0_CONFIG_SDA 1
218#define TWI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
220#define TWI0_INSTANCE_INDEX 0
223#define TWI1_ENABLED 0
225#if (TWI1_ENABLED == 1)
226#define TWI1_CONFIG_FREQUENCY NRF_TWI_FREQ_100K
227#define TWI1_CONFIG_SCL 0
228#define TWI1_CONFIG_SDA 1
229#define TWI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
231#define TWI1_INSTANCE_INDEX (TWI0_ENABLED)
234#define TWI_COUNT (TWI0_ENABLED+TWI1_ENABLED)
237#define TWIS0_ENABLED 0
239#if (TWIS0_ENABLED == 1)
240 #define TWIS0_CONFIG_ADDR0 0
241 #define TWIS0_CONFIG_ADDR1 0
242 #define TWIS0_CONFIG_SCL 0
243 #define TWIS0_CONFIG_SDA 1
244 #define TWIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
246 #define TWIS0_INSTANCE_INDEX 0
249#define TWIS1_ENABLED 0
251#if (TWIS1_ENABLED == 1)
252 #define TWIS1_CONFIG_ADDR0 0
253 #define TWIS1_CONFIG_ADDR1 0
254 #define TWIS1_CONFIG_SCL 0
255 #define TWIS1_CONFIG_SDA 1
256 #define TWIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
258 #define TWIS1_INSTANCE_INDEX (TWIS0_ENABLED)
261#define TWIS_COUNT (TWIS0_ENABLED + TWIS1_ENABLED)
263#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
265#define TWIS_NO_SYNC_MODE 0
276#define NRF_TWIS_PATCH_FOR_MPW3 1
280#define QDEC_ENABLED 0
282#if (QDEC_ENABLED == 1)
283#define QDEC_CONFIG_REPORTPER NRF_QDEC_REPORTPER_10
284#define QDEC_CONFIG_SAMPLEPER NRF_QDEC_SAMPLEPER_16384us
285#define QDEC_CONFIG_PIO_A 1
286#define QDEC_CONFIG_PIO_B 2
287#define QDEC_CONFIG_PIO_LED 3
288#define QDEC_CONFIG_LEDPRE 511
289#define QDEC_CONFIG_LEDPOL NRF_QDEC_LEPOL_ACTIVE_HIGH
290#define QDEC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
291#define QDEC_CONFIG_DBFEN false
292#define QDEC_CONFIG_SAMPLE_INTEN false
296#define SAADC_ENABLED 0
298#if (SAADC_ENABLED == 1)
299#define SAADC_CONFIG_RESOLUTION NRF_SAADC_RESOLUTION_10BIT
300#define SAADC_CONFIG_OVERSAMPLE NRF_SAADC_OVERSAMPLE_DISABLED
301#define SAADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
305#define LPCOMP_ENABLED 0
307#if (LPCOMP_ENABLED == 1)
308#define LPCOMP_CONFIG_REFERENCE NRF_LPCOMP_REF_SUPPLY_4_8
309#define LPCOMP_CONFIG_DETECTION NRF_LPCOMP_DETECT_DOWN
310#define LPCOMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
311#define LPCOMP_CONFIG_INPUT NRF_LPCOMP_INPUT_0
317#if (WDT_ENABLED == 1)
318#define WDT_CONFIG_BEHAVIOUR NRF_WDT_BEHAVIOUR_RUN_SLEEP
319#define WDT_CONFIG_RELOAD_VALUE 2000
320#define WDT_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
323#include "nrf_drv_config_validation.h"