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z1-def.h
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1 /*
2  * Copyright (c) 2010, Swedish Institute of Computer Science.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution.
13  * 3. Neither the name of the Institute nor the names of its contributors
14  * may be used to endorse or promote products derived from this software
15  * without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  */
29 
30 /**
31  * \file
32  * Platform configuration for the Z1 platform
33  * \author
34  * Joakim Eriksson <joakime@sics.se>
35  */
36 
37 #ifndef Z1_DEF_H_
38 #define Z1_DEF_H_
39 
40 #include <iomacros.h>
41 
42 /*
43  * Definitions below are dictated by the hardware and not really
44  * changeable!
45  */
46 
47 #define ZOLERTIA_Z1 1 /* Enric */
48 
49 /* 1 len byte, 2 bytes CRC */
50  #define RADIO_PHY_OVERHEAD 3
51  /* 250kbps data rate. One byte = 32us */
52  #define RADIO_BYTE_AIR_TIME 32
53 /* Delay between GO signal and SFD: radio fixed delay + 4Bytes preample + 1B SFD -- 1Byte time is 32us
54  * ~327us + 129preample = 456 us */
55 #define RADIO_DELAY_BEFORE_TX ((unsigned)US_TO_RTIMERTICKS(456))
56 /* Delay between GO signal and start listening
57  * ~50us delay + 129preample + ?? = 183 us */
58 #define RADIO_DELAY_BEFORE_RX ((unsigned)US_TO_RTIMERTICKS(183))
59 /* Delay between the SFD finishes arriving and it is detected in software */
60 #define RADIO_DELAY_BEFORE_DETECT 0
61 
62 #define PLATFORM_HAS_LEDS 1
63 #define PLATFORM_HAS_BUTTON 1
64 #define PLATFORM_HAS_RADIO 1
65 #define PLATFORM_HAS_BATTERY 1
66 
67 /* CPU target speed in Hz */
68 #define F_CPU 8000000uL /* 8MHz by default */
69 
70 /* the low-level radio driver */
71 #define NETSTACK_CONF_RADIO cc2420_driver
72 
73 /* XXX Temporary place for defines that are lacking in mspgcc4's gpio.h */
74 #ifdef __IAR_SYSTEMS_ICC__
75 #ifndef P1SEL2_
76 #define P1SEL2_ (0x0041u) /* Port 1 Selection 2*/
77 DEFC(P1SEL2, P1SEL2_)
78 #endif
79 #ifndef P5SEL2_
80 #define P5SEL2_ (0x0045u) /* Port 5 Selection 2*/
81 DEFC(P5SEL2, P5SEL2_)
82 #endif
83 #else /* __IAR_SYSTEMS_ICC__ */
84 #ifdef __GNUC__
85 #ifndef P1SEL2_
86 #define P1SEL2_ 0x0041 /* Port 1 Selection 2*/
87 sfrb(P1SEL2, P1SEL2_);
88 #endif
89 #ifndef P5SEL2_
90 #define P5SEL2_ 0x0045 /* Port 5 Selection 2*/
91 sfrb(P5SEL2, P5SEL2_);
92 #endif
93 #endif /* __GNUC__ */
94 #endif /* __IAR_SYSTEMS_ICC__ */
95 
96 /*
97  * Definitions below are dictated by the hardware and not really
98  * changeable!
99  */
100 
101 /* LED ports */
102 #ifdef Z1_IS_Z1SP
103 #define LEDS_PxDIR P4DIR
104 #define LEDS_PxOUT P4OUT
105 #define LEDS_CONF_RED 0x04
106 #define LEDS_CONF_GREEN 0x01
107 #define LEDS_CONF_YELLOW 0x80
108 #else
109 #define LEDS_PxDIR P5DIR
110 #define LEDS_PxOUT P5OUT
111 #define LEDS_CONF_RED 0x10
112 #define LEDS_CONF_GREEN 0x40
113 #define LEDS_CONF_YELLOW 0x20
114 #endif /* Z1_IS_Z1SP */
115 
116 #define LEDS_CONF_LEGACY_API 1
117 
118 /* DCO speed resynchronization for more robust UART, etc. */
119 #ifndef DCOSYNCH_CONF_ENABLED
120 #define DCOSYNCH_CONF_ENABLED (!(MAC_CONF_WITH_TSCH)) /* TSCH needs timerB
121 for SFD timestamping */
122 #endif /* DCOSYNCH_CONF_ENABLED */
123 
124 #ifndef CC2420_CONF_SFD_TIMESTAMPS
125 #define CC2420_CONF_SFD_TIMESTAMPS (MAC_CONF_WITH_TSCH) /* TSCH needs SFD timestamping */
126 #endif /* CC2420_CONF_SFD_TIMESTAMPS */
127 
128 #ifndef DCOSYNCH_CONF_PERIOD
129 #define DCOSYNCH_CONF_PERIOD 30
130 #endif /* DCOSYNCH_CONF_PERIOD */
131 
132 #define ROM_ERASE_UNIT_SIZE 512
133 #define XMEM_ERASE_UNIT_SIZE (64 * 1024L)
134 
135 #define CFS_CONF_OFFSET_TYPE long
136 
137 /* Use the first 64k of external flash for node configuration */
138 #define NODE_ID_XMEM_OFFSET (0 * XMEM_ERASE_UNIT_SIZE)
139 
140 /* Use the second 64k of external flash for codeprop. */
141 #define EEPROMFS_ADDR_CODEPROP (1 * XMEM_ERASE_UNIT_SIZE)
142 
143 #define CFS_XMEM_CONF_OFFSET (2 * XMEM_ERASE_UNIT_SIZE)
144 #define CFS_XMEM_CONF_SIZE (1 * XMEM_ERASE_UNIT_SIZE)
145 
146 #define CFS_RAM_CONF_SIZE 4096
147 
148 /*
149  * SPI bus configuration for the Z1 mote.
150  */
151 
152 /* SPI input/output registers. */
153 #define SPI_TXBUF UCB0TXBUF
154 #define SPI_RXBUF UCB0RXBUF
155 
156 /* USART0 Tx ready? */
157 #define SPI_WAITFOREOTx() while((UCB0STAT & UCBUSY) != 0)
158 /* USART0 Rx ready? */
159 #define SPI_WAITFOREORx() while((IFG2 & UCB0RXIFG) == 0)
160 /* USART0 Tx buffer ready? */
161 #define SPI_WAITFORTxREADY() while((IFG2 & UCB0TXIFG) == 0)
162 
163 #define MOSI 1 /* P3.1 - Output: SPI Master out - slave in (MOSI) */
164 #define MISO 2 /* P3.2 - Input: SPI Master in - slave out (MISO) */
165 #define SCK 3 /* P3.3 - Output: SPI Serial Clock (SCLK) */
166 
167 /*
168  * SPI bus - M25P80 external flash configuration.
169  */
170 /* FLASH_PWR P4.3 Output ALWAYS POWERED ON Z1 */
171 #define FLASH_CS 4 /* P4.4 Output */
172 #define FLASH_HOLD 7 /* P5.7 Output */
173 
174 /* Enable/disable flash access to the SPI bus (active low). */
175 
176 #define SPI_FLASH_ENABLE() (P4OUT &= ~BV(FLASH_CS))
177 #define SPI_FLASH_DISABLE() (P4OUT |= BV(FLASH_CS))
178 
179 #define SPI_FLASH_HOLD() (P5OUT &= ~BV(FLASH_HOLD))
180 #define SPI_FLASH_UNHOLD() (P5OUT |= BV(FLASH_HOLD))
181 
182 /*
183  * SPI bus - CC2420 pin configuration.
184  */
185 
186 #define CC2420_CONF_SYMBOL_LOOP_COUNT 1302 /* 326us msp430X @ 8MHz */
187 
188 /* P1.2 - Input: FIFOP from CC2420 */
189 #define CC2420_FIFOP_PORT(type) P1##type
190 #define CC2420_FIFOP_PIN 2
191 /* P1.3 - Input: FIFO from CC2420 */
192 #define CC2420_FIFO_PORT(type) P1##type
193 #define CC2420_FIFO_PIN 3
194 /* P1.4 - Input: CCA from CC2420 */
195 #define CC2420_CCA_PORT(type) P1##type
196 #define CC2420_CCA_PIN 4
197 /* P4.1 - Input: SFD from CC2420 */
198 #define CC2420_SFD_PORT(type) P4##type
199 #define CC2420_SFD_PIN 1
200 /* P3.0 - Output: SPI Chip Select (CS_N) */
201 #define CC2420_CSN_PORT(type) P3##type
202 #define CC2420_CSN_PIN 0
203 /* P4.5 - Output: VREG_EN to CC2420 */
204 #define CC2420_VREG_PORT(type) P4##type
205 #define CC2420_VREG_PIN 5
206 /* P4.6 - Output: RESET_N to CC2420 */
207 #define CC2420_RESET_PORT(type) P4##type
208 #define CC2420_RESET_PIN 6
209 
210 #define CC2420_IRQ_VECTOR PORT1_VECTOR
211 
212 /* Pin status. */
213 #define CC2420_FIFOP_IS_1 (!!(CC2420_FIFOP_PORT(IN) & BV(CC2420_FIFOP_PIN)))
214 #define CC2420_FIFO_IS_1 (!!(CC2420_FIFO_PORT(IN) & BV(CC2420_FIFO_PIN)))
215 #define CC2420_CCA_IS_1 (!!(CC2420_CCA_PORT(IN) & BV(CC2420_CCA_PIN)))
216 #define CC2420_SFD_IS_1 (!!(CC2420_SFD_PORT(IN) & BV(CC2420_SFD_PIN)))
217 
218 /* The CC2420 reset pin. */
219 #define SET_RESET_INACTIVE() (CC2420_RESET_PORT(OUT) |= BV(CC2420_RESET_PIN))
220 #define SET_RESET_ACTIVE() (CC2420_RESET_PORT(OUT) &= ~BV(CC2420_RESET_PIN))
221 
222 /* CC2420 voltage regulator enable pin. */
223 #define SET_VREG_ACTIVE() (CC2420_VREG_PORT(OUT) |= BV(CC2420_VREG_PIN))
224 #define SET_VREG_INACTIVE() (CC2420_VREG_PORT(OUT) &= ~BV(CC2420_VREG_PIN))
225 
226 /* CC2420 rising edge trigger for external interrupt 0 (FIFOP). */
227 #define CC2420_FIFOP_INT_INIT() do { \
228  CC2420_FIFOP_PORT(IES) &= ~BV(CC2420_FIFOP_PIN); \
229  CC2420_CLEAR_FIFOP_INT(); \
230 } while(0)
231 
232 /* FIFOP on external interrupt 0. */
233 #define CC2420_ENABLE_FIFOP_INT() do { CC2420_FIFOP_PORT(IE) |= BV(CC2420_FIFOP_PIN); } while(0)
234 #define CC2420_DISABLE_FIFOP_INT() do { CC2420_FIFOP_PORT(IE) &= ~BV(CC2420_FIFOP_PIN); } while(0)
235 #define CC2420_CLEAR_FIFOP_INT() do { CC2420_FIFOP_PORT(IFG) &= ~BV(CC2420_FIFOP_PIN); } while(0)
236 
237 /*
238  * Enables/disables CC2420 access to the SPI bus (not the bus).
239  * (Chip Select)
240  */
241 
242 /* ENABLE CSn (active low) */
243 #define CC2420_SPI_ENABLE() (CC2420_CSN_PORT(OUT) &= ~BV(CC2420_CSN_PIN))
244 /* DISABLE CSn (active low) */
245 #define CC2420_SPI_DISABLE() (CC2420_CSN_PORT(OUT) |= BV(CC2420_CSN_PIN))
246 #define CC2420_SPI_IS_ENABLED() ((CC2420_CSN_PORT(OUT) & BV(CC2420_CSN_PIN)) != BV(CC2420_CSN_PIN))
247 
248 /*
249  * I2C configuration
250  */
251 
252 #define I2C_PxDIR P5DIR
253 #define I2C_PxIN P5IN
254 #define I2C_PxOUT P5OUT
255 #define I2C_PxSEL P5SEL
256 #define I2C_PxSEL2 P5SEL2
257 #define I2C_PxREN P5REN
258 
259 #define I2C_SDA (1 << 1) /* SDA == P5.1 */
260 #define I2C_SCL (1 << 2) /* SCL == P5.2 */
261 #define I2C_PRESC_1KHZ_LSB 0x00
262 #define I2C_PRESC_1KHZ_MSB 0x20
263 #define I2C_PRESC_100KHZ_LSB 0x50
264 #define I2C_PRESC_100KHZ_MSB 0x00
265 #define I2C_PRESC_400KHZ_LSB 0x14
266 #define I2C_PRESC_400KHZ_MSB 0x00
267 
268 /* Set rate as high as possible by default */
269 #ifndef I2C_PRESC_Z1_LSB
270 #define I2C_PRESC_Z1_LSB I2C_PRESC_400KHZ_LSB
271 #endif
272 
273 #ifndef I2C_PRESC_Z1_MSB
274 #define I2C_PRESC_Z1_MSB I2C_PRESC_400KHZ_MSB
275 #endif
276 
277 /* I2C configuration with RX interrupts */
278 #ifdef I2C_CONF_RX_WITH_INTERRUPT
279 #define I2C_RX_WITH_INTERRUPT I2C_CONF_RX_WITH_INTERRUPT
280 #else /* I2C_CONF_RX_WITH_INTERRUPT */
281 #define I2C_RX_WITH_INTERRUPT 1
282 #endif /* I2C_CONF_RX_WITH_INTERRUPT */
283 
284 /* Platform-specific define for the end of the stack region */
285 #define STACK_CONF_ORIGIN ((void *)0x3100)
286 
287 #endif /* PLATFORM_CONF_H_ */
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