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rfcore-ffsm.h
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1 /*
2  * Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution.
13  *
14  * 3. Neither the name of the copyright holder nor the names of its
15  * contributors may be used to endorse or promote products derived
16  * from this software without specific prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
21  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
22  * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
23  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
27  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
29  * OF THE POSSIBILITY OF SUCH DAMAGE.
30  */
31 /**
32  * \addtogroup cc2538-rfcore
33  * @{
34  *
35  * \file
36  * Header with declarations of the RF Core FFSM registers.
37  */
38 #ifndef RFCORE_FFSM_H_
39 #define RFCORE_FFSM_H_
40 /*---------------------------------------------------------------------------*/
41 /** \name RFCORE_FFSM register offsets
42  * @{
43  */
44 #define RFCORE_FFSM_SRCRESMASK0 0x40088580 /**< Src addr matching result */
45 #define RFCORE_FFSM_SRCRESMASK1 0x40088584 /**< Src addr matching result */
46 #define RFCORE_FFSM_SRCRESMASK2 0x40088588 /**< Src addr matching result */
47 #define RFCORE_FFSM_SRCRESINDEX 0x4008858C /**< Src addr matching result */
48 #define RFCORE_FFSM_SRCEXTPENDEN0 0x40088590 /**< Src addr matching control */
49 #define RFCORE_FFSM_SRCEXTPENDEN1 0x40088594 /**< Src addr matching control */
50 #define RFCORE_FFSM_SRCEXTPENDEN2 0x40088598 /**< Src addr matching control */
51 #define RFCORE_FFSM_SRCSHORTPENDEN0 0x4008859C /**< Src addr matching control */
52 #define RFCORE_FFSM_SRCSHORTPENDEN1 0x400885A0 /**< Src addr matching control */
53 #define RFCORE_FFSM_SRCSHORTPENDEN2 0x400885A4 /**< Src addr matching control */
54 #define RFCORE_FFSM_EXT_ADDR0 0x400885A8 /**< Local address information */
55 #define RFCORE_FFSM_EXT_ADDR1 0x400885AC /**< Local address information */
56 #define RFCORE_FFSM_EXT_ADDR2 0x400885B0 /**< Local address information */
57 #define RFCORE_FFSM_EXT_ADDR3 0x400885B4 /**< Local address information */
58 #define RFCORE_FFSM_EXT_ADDR4 0x400885B8 /**< Local address information */
59 #define RFCORE_FFSM_EXT_ADDR5 0x400885BC /**< Local address information */
60 #define RFCORE_FFSM_EXT_ADDR6 0x400885C0 /**< Local address information */
61 #define RFCORE_FFSM_EXT_ADDR7 0x400885C4 /**< Local address information */
62 #define RFCORE_FFSM_PAN_ID0 0x400885C8 /**< Local address information */
63 #define RFCORE_FFSM_PAN_ID1 0x400885CC /**< Local address information */
64 #define RFCORE_FFSM_SHORT_ADDR0 0x400885D0 /**< Local address information */
65 #define RFCORE_FFSM_SHORT_ADDR1 0x400885D4 /**< Local address information */
66 /** @} */
67 /*---------------------------------------------------------------------------*/
68 /** \name RFCORE_FFSM_SRCRESMASK[0:2] register bit masks
69  * @{
70  */
71 #define RFCORE_FFSM_SRCRESMASK0_SRCRESMASK0 0x000000FF /**< Ext addr match */
72 #define RFCORE_FFSM_SRCRESMASK1_SRCRESMASK1 0x000000FF /**< Short addr match */
73 #define RFCORE_FFSM_SRCRESMASK2_SRCRESMASK2 0x000000FF /**< 24-bit mask */
74 /** @} */
75 /*---------------------------------------------------------------------------*/
76 /** \name RFCORE_FFSM_SRCRESINDEX register bit masks
77  * @{
78  */
79 #define RFCORE_FFSM_SRCRESINDEX_SRCRESINDEX 0x000000FF /**< LS Entry bit index */
80 /** @} */
81 /*---------------------------------------------------------------------------*/
82 /** \name RFCORE_FFSM_SRCEXTPENDEN[0:2] register bit masks
83  * @{
84  */
85 #define RFCORE_FFSM_SRCEXTPENDEN0_SRCEXTPENDEN0 0x000000FF /**< 8 LSBs */
86 #define RFCORE_FFSM_SRCEXTPENDEN1_SRCEXTPENDEN1 0x000000FF /**< 8 middle bits */
87 #define RFCORE_FFSM_SRCEXTPENDEN2_SRCEXTPENDEN2 0x000000FF /**< 8 MSBs */
88 /** @} */
89 /*---------------------------------------------------------------------------*/
90 /** \name RFCORE_FFSM_SRCSHORTPENDEN[0:2] register bit masks
91  * @{
92  */
93 #define RFCORE_FFSM_SRCSHORTPENDEN0_SRCSHORTPENDEN0 0x000000FF /**< 8 LSBs */
94 #define RFCORE_FFSM_SRCSHORTPENDEN1_SRCSHORTPENDEN1 0x000000FF /**< 8 middle */
95 #define RFCORE_FFSM_SRCSHORTPENDEN2_SRCSHORTPENDEN2 0x000000FF /**< 8 MSBs */
96 /** @} */
97 /*---------------------------------------------------------------------------*/
98 /** \name RFCORE_FFSM_EXT_ADDR[0:7] register bit masks
99  * @{
100  */
101 #define RFCORE_FFSM_EXT_ADDR0_EXT_ADDR0 0x000000FF /**< EXT_ADDR[7:0] */
102 #define RFCORE_FFSM_EXT_ADDR1_EXT_ADDR1 0x000000FF /**< EXT_ADDR[15:8] */
103 #define RFCORE_FFSM_EXT_ADDR2_EXT_ADDR2 0x000000FF /**< EXT_ADDR[23:16] */
104 #define RFCORE_FFSM_EXT_ADDR3_EXT_ADDR3 0x000000FF /**< EXT_ADDR[31:24] */
105 #define RFCORE_FFSM_EXT_ADDR4_EXT_ADDR4 0x000000FF /**< EXT_ADDR[39:32] */
106 #define RFCORE_FFSM_EXT_ADDR5_EXT_ADDR5 0x000000FF /**< EXT_ADDR[47:40] */
107 #define RFCORE_FFSM_EXT_ADDR6_EXT_ADDR6 0x000000FF /**< EXT_ADDR[55:48] */
108 #define RFCORE_FFSM_EXT_ADDR7_EXT_ADDR7 0x000000FF /**< EXT_ADDR[63:56] */
109 /** @} */
110 /*---------------------------------------------------------------------------*/
111 /** \name RFCORE_FFSM_PAN_ID[0:1] register bit masks
112  * @{
113  */
114 #define RFCORE_FFSM_PAN_ID0_PAN_ID0 0x000000FF /**< PAN_ID[7:0] */
115 #define RFCORE_FFSM_PAN_ID1_PAN_ID1 0x000000FF /**< PAN_ID[15:8] */
116 /** @} */
117 /*---------------------------------------------------------------------------*/
118 /** \name RFCORE_FFSM_SHORT_ADDR[0:1] register bit masks
119  * @{
120  */
121 #define RFCORE_FFSM_SHORT_ADDR0_SHORT_ADDR0 0x000000FF /**< SHORT_ADDR[7:0] */
122 #define RFCORE_FFSM_SHORT_ADDR1_SHORT_ADDR1 0x000000FF /**< SHORT_ADDR[15:8] */
123 /** @} */
124 
125 #endif /* RFCORE_FFSM_H_ */
126 /** @} */