Contiki-NG
nrf_drv_config.h
1 /*
2  * Copyright (c) 2015, Nordic Semiconductor
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution.
13  * 3. Neither the name of the Institute nor the names of its contributors
14  * may be used to endorse or promote products derived from this software
15  * without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  *
29  */
30 
31 /**
32  * \addtogroup nrf52dk
33  * @{
34  *
35  * \defgroup nrf52dk-config nRF52 SDK configuration
36  * @{
37  */
38 
39 #ifndef NRF_DRV_CONFIG_H
40 #define NRF_DRV_CONFIG_H
41 
42 /* CLOCK */
43 #define CLOCK_CONFIG_XTAL_FREQ NRF_CLOCK_XTALFREQ_Default
44 #define CLOCK_CONFIG_LF_SRC NRF_CLOCK_LF_SRC_Xtal
45 #define CLOCK_CONFIG_LF_RC_CAL_INTERVAL RC_2000MS_CALIBRATION_INTERVAL
46 #define CLOCK_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
47 
48 /* GPIOTE */
49 #define GPIOTE_ENABLED 1
50 
51 #if (GPIOTE_ENABLED == 1)
52 #define GPIOTE_CONFIG_USE_SWI_EGU false
53 #define GPIOTE_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
54 #define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 4
55 #endif
56 
57 /* TIMER */
58 #define TIMER0_ENABLED 0
59 
60 #if (TIMER0_ENABLED == 1)
61 #define TIMER0_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
62 #define TIMER0_CONFIG_MODE TIMER_MODE_MODE_Timer
63 #define TIMER0_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_32Bit
64 #define TIMER0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
65 
66 #define TIMER0_INSTANCE_INDEX 0
67 #endif
68 
69 #define TIMER1_ENABLED 1
70 
71 #if (TIMER1_ENABLED == 1)
72 #define TIMER1_CONFIG_FREQUENCY NRF_TIMER_FREQ_62500Hz
73 #define TIMER1_CONFIG_MODE TIMER_MODE_MODE_Timer
74 #define TIMER1_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_32Bit
75 #define TIMER1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
76 
77 #define TIMER1_INSTANCE_INDEX (TIMER0_ENABLED)
78 #endif
79 
80 #define TIMER2_ENABLED 0
81 
82 #if (TIMER2_ENABLED == 1)
83 #define TIMER2_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
84 #define TIMER2_CONFIG_MODE TIMER_MODE_MODE_Timer
85 #define TIMER2_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
86 #define TIMER2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
87 
88 #define TIMER2_INSTANCE_INDEX (TIMER1_ENABLED+TIMER0_ENABLED)
89 #endif
90 
91 #define TIMER3_ENABLED 0
92 
93 #if (TIMER3_ENABLED == 1)
94 #define TIMER3_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
95 #define TIMER3_CONFIG_MODE TIMER_MODE_MODE_Timer
96 #define TIMER3_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
97 #define TIMER3_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
98 
99 #define TIMER3_INSTANCE_INDEX (TIMER2_ENABLED+TIMER2_INSTANCE_INDEX)
100 #endif
101 
102 #define TIMER4_ENABLED 0
103 
104 #if (TIMER4_ENABLED == 1)
105 #define TIMER4_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
106 #define TIMER4_CONFIG_MODE TIMER_MODE_MODE_Timer
107 #define TIMER4_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
108 #define TIMER4_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
109 
110 #define TIMER4_INSTANCE_INDEX (TIMER3_ENABLED+TIMER3_INSTANCE_INDEX)
111 #endif
112 
113 
114 #define TIMER_COUNT (TIMER0_ENABLED + TIMER1_ENABLED + TIMER2_ENABLED + TIMER3_ENABLED + TIMER4_ENABLED)
115 
116 /* RTC */
117 #define RTC0_ENABLED 0
118 
119 #if (RTC0_ENABLED == 1)
120 #define RTC0_CONFIG_FREQUENCY 32678
121 #define RTC0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
122 #define RTC0_CONFIG_RELIABLE false
123 
124 #define RTC0_INSTANCE_INDEX 0
125 #endif
126 
127 #define RTC1_ENABLED 1
128 
129 #if (RTC1_ENABLED == 1)
130 #define RTC1_CONFIG_FREQUENCY 128
131 #define RTC1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
132 #define RTC1_CONFIG_RELIABLE false
133 
134 #define RTC1_INSTANCE_INDEX (RTC0_ENABLED)
135 #endif
136 
137 #define RTC_COUNT (RTC0_ENABLED+RTC1_ENABLED)
138 
139 #define NRF_MAXIMUM_LATENCY_US 2000
140 
141 /* RNG */
142 #define RNG_ENABLED 1
143 
144 #if (RNG_ENABLED == 1)
145 #define RNG_CONFIG_ERROR_CORRECTION true
146 #define RNG_CONFIG_POOL_SIZE 8
147 #define RNG_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
148 #endif
149 
150 /* SPI */
151 #define SPI0_ENABLED 0
152 
153 #if (SPI0_ENABLED == 1)
154 #define SPI0_USE_EASY_DMA 0
155 
156 #define SPI0_CONFIG_SCK_PIN 2
157 #define SPI0_CONFIG_MOSI_PIN 3
158 #define SPI0_CONFIG_MISO_PIN 4
159 #define SPI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
160 
161 #define SPI0_INSTANCE_INDEX 0
162 #endif
163 
164 #define SPI1_ENABLED 0
165 
166 #if (SPI1_ENABLED == 1)
167 #define SPI1_USE_EASY_DMA 0
168 
169 #define SPI1_CONFIG_SCK_PIN 2
170 #define SPI1_CONFIG_MOSI_PIN 3
171 #define SPI1_CONFIG_MISO_PIN 4
172 #define SPI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
173 
174 #define SPI1_INSTANCE_INDEX (SPI0_ENABLED)
175 #endif
176 
177 #define SPI2_ENABLED 0
178 
179 #if (SPI2_ENABLED == 1)
180 #define SPI2_USE_EASY_DMA 0
181 
182 #define SPI2_CONFIG_SCK_PIN 2
183 #define SPI2_CONFIG_MOSI_PIN 3
184 #define SPI2_CONFIG_MISO_PIN 4
185 #define SPI2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
186 
187 #define SPI2_INSTANCE_INDEX (SPI0_ENABLED + SPI1_ENABLED)
188 #endif
189 
190 #define SPI_COUNT (SPI0_ENABLED + SPI1_ENABLED + SPI2_ENABLED)
191 
192 /* UART */
193 #define UART0_ENABLED 1
194 
195 #if (UART0_ENABLED == 1)
196 #define UART0_CONFIG_HWFC NRF_UART_HWFC_DISABLED
197 #define UART0_CONFIG_PARITY NRF_UART_PARITY_EXCLUDED
198 #define UART0_CONFIG_BAUDRATE NRF_UART_BAUDRATE_115200
199 #define UART0_CONFIG_PSEL_TXD 6
200 #define UART0_CONFIG_PSEL_RXD 8
201 #define UART0_CONFIG_PSEL_CTS 7
202 #define UART0_CONFIG_PSEL_RTS 5
203 #define UART0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
204 #ifdef NRF52
205 #define UART0_CONFIG_USE_EASY_DMA false
206 //Compile time flag
207 #define UART_EASY_DMA_SUPPORT 1
208 #define UART_LEGACY_SUPPORT 1
209 #endif //NRF52
210 #endif
211 
212 #define TWI0_ENABLED 0
213 
214 #if (TWI0_ENABLED == 1)
215 #define TWI0_CONFIG_FREQUENCY NRF_TWI_FREQ_100K
216 #define TWI0_CONFIG_SCL 0
217 #define TWI0_CONFIG_SDA 1
218 #define TWI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
219 
220 #define TWI0_INSTANCE_INDEX 0
221 #endif
222 
223 #define TWI1_ENABLED 0
224 
225 #if (TWI1_ENABLED == 1)
226 #define TWI1_CONFIG_FREQUENCY NRF_TWI_FREQ_100K
227 #define TWI1_CONFIG_SCL 0
228 #define TWI1_CONFIG_SDA 1
229 #define TWI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
230 
231 #define TWI1_INSTANCE_INDEX (TWI0_ENABLED)
232 #endif
233 
234 #define TWI_COUNT (TWI0_ENABLED+TWI1_ENABLED)
235 
236 /* TWIS */
237 #define TWIS0_ENABLED 0
238 
239 #if (TWIS0_ENABLED == 1)
240  #define TWIS0_CONFIG_ADDR0 0
241  #define TWIS0_CONFIG_ADDR1 0 /* 0: Disabled */
242  #define TWIS0_CONFIG_SCL 0
243  #define TWIS0_CONFIG_SDA 1
244  #define TWIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
245 
246  #define TWIS0_INSTANCE_INDEX 0
247 #endif
248 
249 #define TWIS1_ENABLED 0
250 
251 #if (TWIS1_ENABLED == 1)
252  #define TWIS1_CONFIG_ADDR0 0
253  #define TWIS1_CONFIG_ADDR1 0 /* 0: Disabled */
254  #define TWIS1_CONFIG_SCL 0
255  #define TWIS1_CONFIG_SDA 1
256  #define TWIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
257 
258  #define TWIS1_INSTANCE_INDEX (TWIS0_ENABLED)
259 #endif
260 
261 #define TWIS_COUNT (TWIS0_ENABLED + TWIS1_ENABLED)
262 /* For more documentation see nrf_drv_twis.h file */
263 #define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
264 /* For more documentation see nrf_drv_twis.h file */
265 #define TWIS_NO_SYNC_MODE 0
266 /**
267  * \brief Definition for patching PAN problems
268  *
269  * Set this definition to nonzero value to patch anomalies
270  * from MPW3 - first lunch microcontroller.
271  *
272  * Concerns:
273  * - PAN-29: TWIS: incorrect bits in ERRORSRC
274  * - PAN-30: TWIS: STOP task does not work as expected
275  */
276 #define NRF_TWIS_PATCH_FOR_MPW3 1
277 
278 
279 /* QDEC */
280 #define QDEC_ENABLED 0
281 
282 #if (QDEC_ENABLED == 1)
283 #define QDEC_CONFIG_REPORTPER NRF_QDEC_REPORTPER_10
284 #define QDEC_CONFIG_SAMPLEPER NRF_QDEC_SAMPLEPER_16384us
285 #define QDEC_CONFIG_PIO_A 1
286 #define QDEC_CONFIG_PIO_B 2
287 #define QDEC_CONFIG_PIO_LED 3
288 #define QDEC_CONFIG_LEDPRE 511
289 #define QDEC_CONFIG_LEDPOL NRF_QDEC_LEPOL_ACTIVE_HIGH
290 #define QDEC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
291 #define QDEC_CONFIG_DBFEN false
292 #define QDEC_CONFIG_SAMPLE_INTEN false
293 #endif
294 
295 /* SAADC */
296 #define SAADC_ENABLED 0
297 
298 #if (SAADC_ENABLED == 1)
299 #define SAADC_CONFIG_RESOLUTION NRF_SAADC_RESOLUTION_10BIT
300 #define SAADC_CONFIG_OVERSAMPLE NRF_SAADC_OVERSAMPLE_DISABLED
301 #define SAADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
302 #endif
303 
304 /* LPCOMP */
305 #define LPCOMP_ENABLED 0
306 
307 #if (LPCOMP_ENABLED == 1)
308 #define LPCOMP_CONFIG_REFERENCE NRF_LPCOMP_REF_SUPPLY_4_8
309 #define LPCOMP_CONFIG_DETECTION NRF_LPCOMP_DETECT_DOWN
310 #define LPCOMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
311 #define LPCOMP_CONFIG_INPUT NRF_LPCOMP_INPUT_0
312 #endif
313 
314 /* WDT */
315 #define WDT_ENABLED 1
316 
317 #if (WDT_ENABLED == 1)
318 #define WDT_CONFIG_BEHAVIOUR NRF_WDT_BEHAVIOUR_RUN_SLEEP
319 #define WDT_CONFIG_RELOAD_VALUE 2000
320 #define WDT_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
321 #endif
322 
323 #include "nrf_drv_config_validation.h"
324 #endif // NRF_DRV_CONFIG_H
325 
326 /**
327  * @}
328  * @}
329  */