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Structure type to access the Trace Port Interface Register (TPI). More...
#include <arch/cpu/arm/cortex-m/CMSIS/core_cm3.h>
Data Fields | |
__IOM uint32_t | SSPSR |
__IOM uint32_t | CSPSR |
__IOM uint32_t | ACPR |
__IOM uint32_t | SPPR |
__IM uint32_t | FFSR |
__IOM uint32_t | FFCR |
__IM uint32_t | FSCR |
__IM uint32_t | TRIGGER |
__IM uint32_t | FIFO0 |
__IM uint32_t | ITATBCTR2 |
__IM uint32_t | ITATBCTR0 |
__IM uint32_t | FIFO1 |
__IOM uint32_t | ITCTRL |
__IOM uint32_t | CLAIMSET |
__IOM uint32_t | CLAIMCLR |
__IM uint32_t | DEVID |
__IM uint32_t | DEVTYPE |
Structure type to access the Trace Port Interface Register (TPI).
Definition at line 985 of file core_cm3.h.
__IOM uint32_t TPI_Type::ACPR |
Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register
Definition at line 990 of file core_cm3.h.
__IOM uint32_t TPI_Type::CLAIMCLR |
Offset: 0xFA4 (R/W) Claim tag clear
Definition at line 1007 of file core_cm3.h.
__IOM uint32_t TPI_Type::CLAIMSET |
Offset: 0xFA0 (R/W) Claim tag set
Definition at line 1006 of file core_cm3.h.
__IOM uint32_t TPI_Type::CSPSR |
Offset: 0x004 (R/W) Current Parallel Port Size Register
Definition at line 988 of file core_cm3.h.
__IM uint32_t TPI_Type::DEVID |
Offset: 0xFC8 (R/ ) TPIU_DEVID
Definition at line 1009 of file core_cm3.h.
__IM uint32_t TPI_Type::DEVTYPE |
Offset: 0xFCC (R/ ) TPIU_DEVTYPE
Definition at line 1010 of file core_cm3.h.
__IOM uint32_t TPI_Type::FFCR |
Offset: 0x304 (R/W) Formatter and Flush Control Register
Definition at line 995 of file core_cm3.h.
__IM uint32_t TPI_Type::FFSR |
Offset: 0x300 (R/ ) Formatter and Flush Status Register
Definition at line 994 of file core_cm3.h.
__IM uint32_t TPI_Type::FIFO0 |
Offset: 0xEEC (R/ ) Integration ETM Data
Definition at line 999 of file core_cm3.h.
__IM uint32_t TPI_Type::FIFO1 |
Offset: 0xEFC (R/ ) Integration ITM Data
Definition at line 1003 of file core_cm3.h.
__IM uint32_t TPI_Type::FSCR |
Offset: 0x308 (R/ ) Formatter Synchronization Counter Register
Definition at line 996 of file core_cm3.h.
__IM uint32_t TPI_Type::ITATBCTR0 |
Offset: 0xEF8 (R/ ) ITATBCTR0
Definition at line 1002 of file core_cm3.h.
__IM uint32_t TPI_Type::ITATBCTR2 |
Offset: 0xEF0 (R/ ) ITATBCTR2
Definition at line 1000 of file core_cm3.h.
__IOM uint32_t TPI_Type::ITCTRL |
Offset: 0xF00 (R/W) Integration Mode Control
Definition at line 1004 of file core_cm3.h.
__IOM uint32_t TPI_Type::SPPR |
Offset: 0x0F0 (R/W) Selected Pin Protocol Register
Definition at line 992 of file core_cm3.h.
__IOM uint32_t TPI_Type::SSPSR |
Offset: 0x000 (R/ ) Supported Parallel Port Size Register
Definition at line 987 of file core_cm3.h.
__IM uint32_t TPI_Type::TRIGGER |
Offset: 0xEE8 (R/ ) TRIGGER
Definition at line 998 of file core_cm3.h.