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Data Fields

Structure type to access the Data Watchpoint and Trace Register (DWT). More...

#include <arch/cpu/arm/cortex-m/CMSIS/core_cm3.h>

Data Fields

__IOM uint32_t CTRL
 
__IOM uint32_t CYCCNT
 
__IOM uint32_t CPICNT
 
__IOM uint32_t EXCCNT
 
__IOM uint32_t SLEEPCNT
 
__IOM uint32_t LSUCNT
 
__IOM uint32_t FOLDCNT
 
__IM uint32_t PCSR
 
__IOM uint32_t COMP0
 
__IOM uint32_t MASK0
 
__IOM uint32_t FUNCTION0
 
__IOM uint32_t COMP1
 
__IOM uint32_t MASK1
 
__IOM uint32_t FUNCTION1
 
__IOM uint32_t COMP2
 
__IOM uint32_t MASK2
 
__IOM uint32_t FUNCTION2
 
__IOM uint32_t COMP3
 
__IOM uint32_t MASK3
 
__IOM uint32_t FUNCTION3
 
__OM uint32_t LAR
 
__IM uint32_t LSR
 

Detailed Description

Structure type to access the Data Watchpoint and Trace Register (DWT).

Definition at line 838 of file core_cm3.h.

Field Documentation

◆ COMP0

__IOM uint32_t DWT_Type::COMP0

Offset: 0x020 (R/W) Comparator Register 0

Definition at line 848 of file core_cm3.h.

◆ COMP1

__IOM uint32_t DWT_Type::COMP1

Offset: 0x030 (R/W) Comparator Register 1

Definition at line 852 of file core_cm3.h.

◆ COMP2

__IOM uint32_t DWT_Type::COMP2

Offset: 0x040 (R/W) Comparator Register 2

Definition at line 856 of file core_cm3.h.

◆ COMP3

__IOM uint32_t DWT_Type::COMP3

Offset: 0x050 (R/W) Comparator Register 3

Definition at line 860 of file core_cm3.h.

◆ CPICNT

__IOM uint32_t DWT_Type::CPICNT

Offset: 0x008 (R/W) CPI Count Register

Definition at line 842 of file core_cm3.h.

◆ CTRL

__IOM uint32_t DWT_Type::CTRL

Offset: 0x000 (R/W) Control Register

Definition at line 840 of file core_cm3.h.

◆ CYCCNT

__IOM uint32_t DWT_Type::CYCCNT

Offset: 0x004 (R/W) Cycle Count Register

Definition at line 841 of file core_cm3.h.

◆ EXCCNT

__IOM uint32_t DWT_Type::EXCCNT

Offset: 0x00C (R/W) Exception Overhead Count Register

Definition at line 843 of file core_cm3.h.

◆ FOLDCNT

__IOM uint32_t DWT_Type::FOLDCNT

Offset: 0x018 (R/W) Folded-instruction Count Register

Definition at line 846 of file core_cm3.h.

◆ FUNCTION0

__IOM uint32_t DWT_Type::FUNCTION0

Offset: 0x028 (R/W) Function Register 0

Definition at line 850 of file core_cm3.h.

◆ FUNCTION1

__IOM uint32_t DWT_Type::FUNCTION1

Offset: 0x038 (R/W) Function Register 1

Definition at line 854 of file core_cm3.h.

◆ FUNCTION2

__IOM uint32_t DWT_Type::FUNCTION2

Offset: 0x048 (R/W) Function Register 2

Definition at line 858 of file core_cm3.h.

◆ FUNCTION3

__IOM uint32_t DWT_Type::FUNCTION3

Offset: 0x058 (R/W) Function Register 3

Definition at line 862 of file core_cm3.h.

◆ LAR

__OM uint32_t DWT_Type::LAR

Offset: 0xFB0 ( W) Lock Access Register

Definition at line 1127 of file core_cm7.h.

◆ LSR

__IM uint32_t DWT_Type::LSR

Offset: 0xFB4 (R ) Lock Status Register

Definition at line 1128 of file core_cm7.h.

◆ LSUCNT

__IOM uint32_t DWT_Type::LSUCNT

Offset: 0x014 (R/W) LSU Count Register

Definition at line 845 of file core_cm3.h.

◆ MASK0

__IOM uint32_t DWT_Type::MASK0

Offset: 0x024 (R/W) Mask Register 0

Definition at line 849 of file core_cm3.h.

◆ MASK1

__IOM uint32_t DWT_Type::MASK1

Offset: 0x034 (R/W) Mask Register 1

Definition at line 853 of file core_cm3.h.

◆ MASK2

__IOM uint32_t DWT_Type::MASK2

Offset: 0x044 (R/W) Mask Register 2

Definition at line 857 of file core_cm3.h.

◆ MASK3

__IOM uint32_t DWT_Type::MASK3

Offset: 0x054 (R/W) Mask Register 3

Definition at line 861 of file core_cm3.h.

◆ PCSR

__IM uint32_t DWT_Type::PCSR

Offset: 0x01C (R/ ) Program Counter Sample Register

Definition at line 847 of file core_cm3.h.

◆ SLEEPCNT

__IOM uint32_t DWT_Type::SLEEPCNT

Offset: 0x010 (R/W) Sleep Count Register

Definition at line 844 of file core_cm3.h.