Contiki-NG
sky-def.h
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1 /*
2  * Copyright (c) 2010, Swedish Institute of Computer Science.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution.
13  * 3. Neither the name of the Institute nor the names of its contributors
14  * may be used to endorse or promote products derived from this software
15  * without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  *
29  */
30 
31 /**
32  * \file
33  * A brief description of what this file is
34  * \author
35  * Niclas Finne <nfi@sics.se>
36  * Joakim Eriksson <joakime@sics.se>
37  */
38 
39 #ifndef SKY_DEF_H_
40 #define SKY_DEF_H_
41 
42 /*
43  * Definitions below are dictated by the hardware and not really
44  * changeable!
45  */
46 
47  /* 1 len byte, 2 bytes CRC */
48  #define RADIO_PHY_OVERHEAD 3
49  /* 250kbps data rate. One byte = 32us */
50  #define RADIO_BYTE_AIR_TIME 32
51 /* Delay between GO signal and SFD: radio fixed delay + 4Bytes preample + 1B SFD -- 1Byte time is 32us
52  * ~327us + 129preample = 456 us */
53 #define RADIO_DELAY_BEFORE_TX ((unsigned)US_TO_RTIMERTICKS(456))
54 /* Delay between GO signal and start listening
55  * ~50us delay + 129preample + ?? = 183 us */
56 #define RADIO_DELAY_BEFORE_RX ((unsigned)US_TO_RTIMERTICKS(183))
57 /* Delay between the SFD finishes arriving and it is detected in software */
58 #define RADIO_DELAY_BEFORE_DETECT 0
59 
60 /* Disable TSCH frame filtering */
61 #define TSCH_CONF_HW_FRAME_FILTERING 0
62 
63 #define PLATFORM_HAS_LEDS 1
64 #define PLATFORM_HAS_BUTTON 1
65 #define PLATFORM_HAS_LIGHT 1
66 #define PLATFORM_HAS_BATTERY 1
67 #define PLATFORM_HAS_SHT11 1
68 #define PLATFORM_HAS_RADIO 1
69 
70 /* CPU target speed in Hz */
71 #define F_CPU 3900000uL /*2457600uL*/
72 
73 /* the low-level radio driver */
74 #define NETSTACK_CONF_RADIO cc2420_driver
75 
76 /* LED ports */
77 #define LEDS_PxDIR P5DIR
78 #define LEDS_PxOUT P5OUT
79 #define LEDS_CONF_RED 0x10
80 #define LEDS_CONF_GREEN 0x20
81 #define LEDS_CONF_YELLOW 0x40
82 
83 #define LEDS_CONF_LEGACY_API 1
84 
85 /* DCO speed resynchronization for more robust UART, etc. */
86 #ifndef DCOSYNCH_CONF_ENABLED
87 #define DCOSYNCH_CONF_ENABLED (!(MAC_CONF_WITH_TSCH)) /* TSCH needs timerB
88 for SFD timestamping */
89 #endif /* DCOSYNCH_CONF_ENABLED */
90 
91 #ifndef CC2420_CONF_SFD_TIMESTAMPS
92 #define CC2420_CONF_SFD_TIMESTAMPS (MAC_CONF_WITH_TSCH) /* TSCH needs SFD timestamping */
93 #endif /* CC2420_CONF_SFD_TIMESTAMPS */
94 
95 #ifndef DCOSYNCH_CONF_PERIOD
96 #define DCOSYNCH_CONF_PERIOD 30
97 #endif /* DCOSYNCH_CONF_PERIOD */
98 
99 #define ROM_ERASE_UNIT_SIZE 512
100 #define XMEM_ERASE_UNIT_SIZE (64*1024L)
101 
102 
103 #define CFS_CONF_OFFSET_TYPE long
104 
105 
106 /* Use the first 64k of external flash for node configuration */
107 #define NODE_ID_XMEM_OFFSET (0 * XMEM_ERASE_UNIT_SIZE)
108 
109 /* Use the second 64k of external flash for codeprop. */
110 #define EEPROMFS_ADDR_CODEPROP (1 * XMEM_ERASE_UNIT_SIZE)
111 
112 #define CFS_XMEM_CONF_OFFSET (2 * XMEM_ERASE_UNIT_SIZE)
113 #define CFS_XMEM_CONF_SIZE (1 * XMEM_ERASE_UNIT_SIZE)
114 
115 #define CFS_RAM_CONF_SIZE 4096
116 
117 /*
118  * SPI bus configuration for the TMote Sky.
119  */
120 
121 /* SPI input/output registers. */
122 #define SPI_TXBUF U0TXBUF
123 #define SPI_RXBUF U0RXBUF
124 
125  /* USART0 Tx ready? */
126 #define SPI_WAITFOREOTx() while ((U0TCTL & TXEPT) == 0)
127  /* USART0 Rx ready? */
128 #define SPI_WAITFOREORx() while ((IFG1 & URXIFG0) == 0)
129  /* USART0 Tx buffer ready? */
130 #define SPI_WAITFORTxREADY() while ((IFG1 & UTXIFG0) == 0)
131 
132 #define SCK 1 /* P3.1 - Output: SPI Serial Clock (SCLK) */
133 #define MOSI 2 /* P3.2 - Output: SPI Master out - slave in (MOSI) */
134 #define MISO 3 /* P3.3 - Input: SPI Master in - slave out (MISO) */
135 
136 /*
137  * SPI bus - M25P80 external flash configuration.
138  */
139 
140 #define FLASH_PWR 3 /* P4.3 Output */
141 #define FLASH_CS 4 /* P4.4 Output */
142 #define FLASH_HOLD 7 /* P4.7 Output */
143 
144 /* Enable/disable flash access to the SPI bus (active low). */
145 
146 #define SPI_FLASH_ENABLE() ( P4OUT &= ~BV(FLASH_CS) )
147 #define SPI_FLASH_DISABLE() ( P4OUT |= BV(FLASH_CS) )
148 
149 #define SPI_FLASH_HOLD() ( P4OUT &= ~BV(FLASH_HOLD) )
150 #define SPI_FLASH_UNHOLD() ( P4OUT |= BV(FLASH_HOLD) )
151 
152 /*
153  * SPI bus - CC2420 pin configuration.
154  */
155 
156 #define CC2420_CONF_SYMBOL_LOOP_COUNT 800
157 
158 /* P1.0 - Input: FIFOP from CC2420 */
159 #define CC2420_FIFOP_PORT(type) P1##type
160 #define CC2420_FIFOP_PIN 0
161 /* P1.3 - Input: FIFO from CC2420 */
162 #define CC2420_FIFO_PORT(type) P1##type
163 #define CC2420_FIFO_PIN 3
164 /* P1.4 - Input: CCA from CC2420 */
165 #define CC2420_CCA_PORT(type) P1##type
166 #define CC2420_CCA_PIN 4
167 /* P4.1 - Input: SFD from CC2420 */
168 #define CC2420_SFD_PORT(type) P4##type
169 #define CC2420_SFD_PIN 1
170 /* P4.2 - Output: SPI Chip Select (CS_N) */
171 #define CC2420_CSN_PORT(type) P4##type
172 #define CC2420_CSN_PIN 2
173 /* P4.5 - Output: VREG_EN to CC2420 */
174 #define CC2420_VREG_PORT(type) P4##type
175 #define CC2420_VREG_PIN 5
176 /* P4.6 - Output: RESET_N to CC2420 */
177 #define CC2420_RESET_PORT(type) P4##type
178 #define CC2420_RESET_PIN 6
179 
180 #define CC2420_IRQ_VECTOR PORT1_VECTOR
181 
182 /* Pin status. */
183 #define CC2420_FIFOP_IS_1 (!!(CC2420_FIFOP_PORT(IN) & BV(CC2420_FIFOP_PIN)))
184 #define CC2420_FIFO_IS_1 (!!(CC2420_FIFO_PORT(IN) & BV(CC2420_FIFO_PIN)))
185 #define CC2420_CCA_IS_1 (!!(CC2420_CCA_PORT(IN) & BV(CC2420_CCA_PIN)))
186 #define CC2420_SFD_IS_1 (!!(CC2420_SFD_PORT(IN) & BV(CC2420_SFD_PIN)))
187 
188 /* The CC2420 reset pin. */
189 #define SET_RESET_INACTIVE() (CC2420_RESET_PORT(OUT) |= BV(CC2420_RESET_PIN))
190 #define SET_RESET_ACTIVE() (CC2420_RESET_PORT(OUT) &= ~BV(CC2420_RESET_PIN))
191 
192 /* CC2420 voltage regulator enable pin. */
193 #define SET_VREG_ACTIVE() (CC2420_VREG_PORT(OUT) |= BV(CC2420_VREG_PIN))
194 #define SET_VREG_INACTIVE() (CC2420_VREG_PORT(OUT) &= ~BV(CC2420_VREG_PIN))
195 
196 /* CC2420 rising edge trigger for external interrupt 0 (FIFOP). */
197 #define CC2420_FIFOP_INT_INIT() do { \
198  CC2420_FIFOP_PORT(IES) &= ~BV(CC2420_FIFOP_PIN); \
199  CC2420_CLEAR_FIFOP_INT(); \
200  } while(0)
201 
202 /* FIFOP on external interrupt 0. */
203 #define CC2420_ENABLE_FIFOP_INT() do {CC2420_FIFOP_PORT(IE) |= BV(CC2420_FIFOP_PIN);} while(0)
204 #define CC2420_DISABLE_FIFOP_INT() do {CC2420_FIFOP_PORT(IE) &= ~BV(CC2420_FIFOP_PIN);} while(0)
205 #define CC2420_CLEAR_FIFOP_INT() do {CC2420_FIFOP_PORT(IFG) &= ~BV(CC2420_FIFOP_PIN);} while(0)
206 
207 /*
208  * Enables/disables CC2420 access to the SPI bus (not the bus).
209  * (Chip Select)
210  */
211 
212  /* ENABLE CSn (active low) */
213 #define CC2420_SPI_ENABLE() (CC2420_CSN_PORT(OUT) &= ~BV(CC2420_CSN_PIN))
214  /* DISABLE CSn (active low) */
215 #define CC2420_SPI_DISABLE() (CC2420_CSN_PORT(OUT) |= BV(CC2420_CSN_PIN))
216 #define CC2420_SPI_IS_ENABLED() ((CC2420_CSN_PORT(OUT) & BV(CC2420_CSN_PIN)) != BV(CC2420_CSN_PIN))
217 
218 /* Platform-specific define for the end of the stack region */
219 #define STACK_CONF_ORIGIN ((void *)0x3900)
220 
221 #endif /* SKY_DEF_H_ */