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rfcore-sfr.h
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1 /*
2  * Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution.
13  *
14  * 3. Neither the name of the copyright holder nor the names of its
15  * contributors may be used to endorse or promote products derived
16  * from this software without specific prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
21  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
22  * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
23  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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27  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
29  * OF THE POSSIBILITY OF SUCH DAMAGE.
30  */
31 /**
32  * \addtogroup cc2538-rfcore
33  * @{
34  *
35  * \file
36  * Header with declarations of the RF Core SFR registers. Includes
37  * declarations of MAC timer registers.
38  */
39 #ifndef RFCORE_SFR_H_
40 #define RFCORE_SFR_H_
41 /*---------------------------------------------------------------------------*/
42 /** \name RFCORE_SFR register offsets (MAC Timer)
43  * @{
44  */
45 #define RFCORE_SFR_MTCSPCFG 0x40088800 /**< MAC Timer event configuration */
46 #define RFCORE_SFR_MTCTRL 0x40088804 /**< MAC Timer control register */
47 #define RFCORE_SFR_MTIRQM 0x40088808 /**< MAC Timer interrupt mask */
48 #define RFCORE_SFR_MTIRQF 0x4008880C /**< MAC Timer interrupt flags */
49 #define RFCORE_SFR_MTMSEL 0x40088810 /**< MAC Timer multiplex select */
50 #define RFCORE_SFR_MTM0 0x40088814 /**< MAC Timer MUX register 0 */
51 #define RFCORE_SFR_MTM1 0x40088818 /**< MAC Timer MUX register 1 */
52 #define RFCORE_SFR_MTMOVF2 0x4008881C /**< MAC Timer MUX overflow 2 */
53 #define RFCORE_SFR_MTMOVF1 0x40088820 /**< MAC Timer MUX overflow 1 */
54 #define RFCORE_SFR_MTMOVF0 0x40088824 /**< MAC Timer MUX overflow 0 */
55 /** @} */
56 /*---------------------------------------------------------------------------*/
57 /** \name RFCORE_SFR register offsets (RF)
58  * @{
59  */
60 #define RFCORE_SFR_RFDATA 0x40088828 /**< TX/RX FIFO data */
61 #define RFCORE_SFR_RFERRF 0x4008882C /**< RF error interrupt flags */
62 #define RFCORE_SFR_RFIRQF1 0x40088830 /**< RF interrupt flags */
63 #define RFCORE_SFR_RFIRQF0 0x40088834 /**< RF interrupt flags */
64 #define RFCORE_SFR_RFST 0x40088838 /**< RF CSMA-CA/strobe processor */
65 /** @} */
66 /*---------------------------------------------------------------------------*/
67 /** \name RFCORE_SFR_MTCSPCFG register bit masks
68  * @{
69  */
70 #define RFCORE_SFR_MTCSPCFG_MACTIMER_EVENMT_CFG 0x00000070 /**< MT_EVENT2 pulse event trigger */
71 #define RFCORE_SFR_MTCSPCFG_MACTIMER_EVENT1_CFG 0x00000007 /**< MT_EVENT1 pulse event trigger */
72 /** @} */
73 /*---------------------------------------------------------------------------*/
74 /** \name RFCORE_SFR_MTCTRL register bit masks
75  * @{
76  */
77 #define RFCORE_SFR_MTCTRL_LATCH_MODE 0x00000008 /**< OVF counter latch mode */
78 #define RFCORE_SFR_MTCTRL_STATE 0x00000004 /**< State of MAC Timer */
79 #define RFCORE_SFR_MTCTRL_SYNC 0x00000002 /**< Timer start/stop timing */
80 #define RFCORE_SFR_MTCTRL_RUN 0x00000001 /**< Timer start/stop */
81 /** @} */
82 /*---------------------------------------------------------------------------*/
83 /** \name RFCORE_SFR_MTIRQM register bit masks
84  * @{
85  */
86 #define RFCORE_SFR_MTIRQM_MACTIMER_OVF_COMPARE2M 0x00000020 /**< MACTIMER_OVF_COMPARE2 mask */
87 #define RFCORE_SFR_MTIRQM_MACTIMER_OVF_COMPARE1M 0x00000010 /**< MACTIMER_OVF_COMPARE1 mask */
88 #define RFCORE_SFR_MTIRQM_MACTIMER_OVF_PERM 0x00000008 /**< MACTIMER_OVF_PER mask */
89 #define RFCORE_SFR_MTIRQM_MACTIMER_COMPARE2M 0x00000004 /**< MACTIMER_COMPARE2 mask */
90 #define RFCORE_SFR_MTIRQM_MACTIMER_COMPARE1M 0x00000002 /**< MACTIMER_COMPARE1 mask */
91 #define RFCORE_SFR_MTIRQM_MACTIMER_PERM 0x00000001 /**< MACTIMER_PER mask */
92 /** @} */
93 /*---------------------------------------------------------------------------*/
94 /** \name RFCORE_SFR_MTIRQF register bit masks
95  * @{
96  */
97 #define RFCORE_SFR_MTIRQF_MACTIMER_OVF_COMPARE2F 0x00000020 /**< MACTIMER_OVF_COMPARE2 flag */
98 #define RFCORE_SFR_MTIRQF_MACTIMER_OVF_COMPARE1F 0x00000010 /**< MACTIMER_OVF_COMPARE1 flag */
99 #define RFCORE_SFR_MTIRQF_MACTIMER_OVF_PERF 0x00000008 /**< MACTIMER_OVF_PER flag */
100 #define RFCORE_SFR_MTIRQF_MACTIMER_COMPARE2F 0x00000004 /**< MACTIMER_COMPARE2 flag */
101 #define RFCORE_SFR_MTIRQF_MACTIMER_COMPARE1F 0x00000002 /**< MACTIMER_COMPARE1 flag */
102 #define RFCORE_SFR_MTIRQF_MACTIMER_PERF 0x00000001 /**< MACTIMER_PER flag */
103 /** @} */
104 /*---------------------------------------------------------------------------*/
105 /** \name RFCORE_SFR_MTMSEL register bit masks
106  * @{
107  */
108 #define RFCORE_SFR_MTMSEL_MTMOVFSEL 0x00000070 /**< MTMOVF register select */
109 #define RFCORE_SFR_MTMSEL_MTMSEL 0x00000007 /**< MTM register select */
110 /** @} */
111 /*---------------------------------------------------------------------------*/
112 /** \name RFCORE_SFR_MTM[0:2] register bit masks
113  * @{
114  */
115 #define RFCORE_SFR_MTM0_MTM0 0x000000FF /**< Register[7:0] */
116 #define RFCORE_SFR_MTM1_MTM1 0x000000FF /**< Register[15:8] */
117 #define RFCORE_SFR_MTMOVF2_MTMOVF2 0x000000FF /**< Register[23:16] */
118 /** @} */
119 /*---------------------------------------------------------------------------*/
120 /** \name RFCORE_SFR_MTMOVF[1:0] register bit masks
121  * @{
122  */
123 #define RFCORE_SFR_MTMOVF1_MTMOVF1 0x000000FF /**< Register[15:8] */
124 #define RFCORE_SFR_MTMOVF0_MTMOVF0 0x000000FF /**< Register[7:0] */
125 /** @} */
126 /*---------------------------------------------------------------------------*/
127 /** \name RFCORE_SFR_RFDATA register bit masks
128  * @{
129  */
130 #define RFCORE_SFR_RFDATA_RFD 0x000000FF /**< Read/Write Data from RF FIFO */
131 /** @} */
132 /*---------------------------------------------------------------------------*/
133 /** \name RFCORE_SFR_RFERRF register bit masks
134  * @{
135  */
136 #define RFCORE_SFR_RFERRF_STROBEERR 0x00000040 /**< Strobe error */
137 #define RFCORE_SFR_RFERRF_TXUNDERF 0x00000020 /**< TX FIFO underflowed */
138 #define RFCORE_SFR_RFERRF_TXOVERF 0x00000010 /**< TX FIFO overflowed */
139 #define RFCORE_SFR_RFERRF_RXUNDERF 0x00000008 /**< RX FIFO underflowed */
140 #define RFCORE_SFR_RFERRF_RXOVERF 0x00000004 /**< RX FIFO overflowed */
141 #define RFCORE_SFR_RFERRF_RXABO 0x00000002 /**< Frame RX was aborted */
142 #define RFCORE_SFR_RFERRF_NLOCK 0x00000001 /**< Frequency synthesizer lock error */
143 /** @} */
144 /*---------------------------------------------------------------------------*/
145 /** \name RFCORE_SFR_RFIRQF1 register bit masks
146  * @{
147  */
148 #define RFCORE_SFR_RFIRQF1_CSP_WAIT 0x00000020 /**< CSP Execution continued */
149 #define RFCORE_SFR_RFIRQF1_CSP_STOP 0x00000010 /**< CSP has stopped program */
150 #define RFCORE_SFR_RFIRQF1_CSP_MANINT 0x00000008 /**< CSP Manual interrupt */
151 #define RFCORE_SFR_RFIRQF1_RFIDLE 0x00000004 /**< IDLE state entered */
152 #define RFCORE_SFR_RFIRQF1_TXDONE 0x00000002 /**< Complete frame TX finished */
153 #define RFCORE_SFR_RFIRQF1_TXACKDONE 0x00000001 /**< ACK frame TX finished */
154 /** @} */
155 /*---------------------------------------------------------------------------*/
156 /** \name RFCORE_SFR_RFIRQF0 register bit masks
157  * @{
158  */
159 #define RFCORE_SFR_RFIRQF0_RXMASKZERO 0x00000080 /**< RXENABLE gone all-zero */
160 #define RFCORE_SFR_RFIRQF0_RXPKTDONE 0x00000040 /**< Complete frame RX */
161 #define RFCORE_SFR_RFIRQF0_FRAME_ACCEPTED 0x00000020 /**< Frame has passed frame filter */
162 #define RFCORE_SFR_RFIRQF0_SRC_MATCH_FOUND 0x00000010 /**< Source match is found */
163 #define RFCORE_SFR_RFIRQF0_SRC_MATCH_DONE 0x00000008 /**< Source matching is complete */
164 #define RFCORE_SFR_RFIRQF0_FIFOP 0x00000004 /**< RX FIFO exceeded threshold */
165 #define RFCORE_SFR_RFIRQF0_SFD 0x00000002 /**< SFD TX or RX */
166 #define RFCORE_SFR_RFIRQF0_ACT_UNUSED 0x00000001 /**< Reserved */
167 /** @} */
168 /*---------------------------------------------------------------------------*/
169 /** \name RFCORE_SFR_RFST register bit masks
170  * @{
171  */
172 #define RFCORE_SFR_RFST_INSTR 0x000000FF /**< Data written to this register */
173 /** @} */
174 
175 #endif /* RFCORE_SFR_H_ */
176 /** @} */
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