Contiki-NG
|
Driver for the cc2538 GPIO controller. More...
Files | |
file | gpio.c |
Implementation of the cc2538 GPIO controller. | |
file | gpio.h |
Header file with register and macro declarations for the cc2538 GPIO module. | |
Functions | |
static void | gpio_port_isr (uint8_t port) |
Interrupt service routine for Port port. More... | |
Base addresses for the GPIO register instances | |
#define | GPIO_A_BASE 0x400D9000 |
GPIO_A. | |
#define | GPIO_B_BASE 0x400DA000 |
GPIO_B. | |
#define | GPIO_C_BASE 0x400DB000 |
GPIO_C. | |
#define | GPIO_D_BASE 0x400DC000 |
GPIO_D. | |
Numeric representation of the four GPIO ports | |
#define | GPIO_A_NUM 0 |
GPIO_A: 0. | |
#define | GPIO_B_NUM 1 |
GPIO_B: 1. | |
#define | GPIO_C_NUM 2 |
GPIO_C: 2. | |
#define | GPIO_D_NUM 3 |
GPIO_D: 3. | |
GPIO Manipulation macros | |
#define | GPIO_SET_INPUT(PORT_BASE, PIN_MASK) do { REG((PORT_BASE) + GPIO_DIR) &= ~(PIN_MASK); } while(0) |
Set pins with PIN_MASK of port with PORT_BASE to input. More... | |
#define | GPIO_SET_OUTPUT(PORT_BASE, PIN_MASK) do { REG((PORT_BASE) + GPIO_DIR) |= (PIN_MASK); } while(0) |
Set pins with PIN_MASK of port with PORT_BASE to output. More... | |
#define | GPIO_IS_OUTPUT(PORT_BASE, PIN_MASK) (REG((PORT_BASE) + GPIO_DIR) & (PIN_MASK)) |
Return whether pins with PIN_MASK of port with PORT_BASE are set to output. More... | |
#define | GPIO_SET_PIN(PORT_BASE, PIN_MASK) do { REG((PORT_BASE) + GPIO_DATA + ((PIN_MASK) << 2)) = 0xFF; } while(0) |
Set pins with PIN_MASK of port with PORT_BASE high. More... | |
#define | GPIO_CLR_PIN(PORT_BASE, PIN_MASK) do { REG((PORT_BASE) + GPIO_DATA + ((PIN_MASK) << 2)) = 0x00; } while(0) |
Set pins with PIN_MASK of port with PORT_BASE low. More... | |
#define | GPIO_WRITE_PIN(PORT_BASE, PIN_MASK, value) do { REG((PORT_BASE) + GPIO_DATA + ((PIN_MASK) << 2)) = (value); } while(0) |
Set pins with PIN_MASK of port with PORT_BASE to value. More... | |
#define | GPIO_READ_PIN(PORT_BASE, PIN_MASK) REG((PORT_BASE) + GPIO_DATA + ((PIN_MASK) << 2)) |
Read pins with PIN_MASK of port with PORT_BASE. More... | |
#define | GPIO_DETECT_EDGE(PORT_BASE, PIN_MASK) do { REG((PORT_BASE) + GPIO_IS) &= ~(PIN_MASK); } while(0) |
Set pins with PIN_MASK of port with PORT_BASE to detect edge. More... | |
#define | GPIO_DETECT_LEVEL(PORT_BASE, PIN_MASK) do { REG((PORT_BASE) + GPIO_IS) |= (PIN_MASK); } while(0) |
Set pins with PIN_MASK of port with PORT_BASE to detect level. More... | |
#define | GPIO_TRIGGER_BOTH_EDGES(PORT_BASE, PIN_MASK) do { REG((PORT_BASE) + GPIO_IBE) |= (PIN_MASK); } while(0) |
Set pins with PIN_MASK of port with PORT_BASE to trigger an interrupt on both edges. More... | |
#define | GPIO_TRIGGER_SINGLE_EDGE(PORT_BASE, PIN_MASK) do { REG((PORT_BASE) + GPIO_IBE) &= ~(PIN_MASK); } while(0) |
Set pins with PIN_MASK of port with PORT_BASE to trigger an interrupt on single edge (controlled by GPIO_IEV). More... | |
#define | GPIO_DETECT_RISING(PORT_BASE, PIN_MASK) do { REG((PORT_BASE) + GPIO_IEV) |= (PIN_MASK); } while(0) |
Set pins with PIN_MASK of port with PORT_BASE to trigger an interrupt on rising edge. More... | |
#define | GPIO_DETECT_FALLING(PORT_BASE, PIN_MASK) do { REG((PORT_BASE) + GPIO_IEV) &= ~(PIN_MASK); } while(0) |
Set pins with PIN_MASK of port with PORT_BASE to trigger an interrupt on falling edge. More... | |
#define | GPIO_ENABLE_INTERRUPT(PORT_BASE, PIN_MASK) do { REG((PORT_BASE) + GPIO_IE) |= (PIN_MASK); } while(0) |
Enable interrupt triggering for pins with PIN_MASK of port with PORT_BASE. More... | |
#define | GPIO_DISABLE_INTERRUPT(PORT_BASE, PIN_MASK) do { REG((PORT_BASE) + GPIO_IE) &= ~(PIN_MASK); } while(0) |
Disable interrupt triggering for pins with PIN_MASK of port with PORT_BASE. More... | |
#define | GPIO_GET_RAW_INT_STATUS(PORT_BASE) REG((PORT_BASE) + GPIO_RIS) |
Get raw interrupt status of port with PORT_BASE. More... | |
#define | GPIO_GET_MASKED_INT_STATUS(PORT_BASE) REG((PORT_BASE) + GPIO_MIS) |
Get masked interrupt status of port with PORT_BASE. More... | |
#define | GPIO_CLEAR_INTERRUPT(PORT_BASE, PIN_MASK) do { REG((PORT_BASE) + GPIO_IC) = (PIN_MASK); } while(0) |
Clear interrupt triggering for pins with PIN_MASK of port with PORT_BASE. More... | |
#define | GPIO_PERIPHERAL_CONTROL(PORT_BASE, PIN_MASK) do { REG((PORT_BASE) + GPIO_AFSEL) |= (PIN_MASK); } while(0) |
Configure the pin to be under peripheral control with PIN_MASK of port with PORT_BASE. More... | |
#define | GPIO_SOFTWARE_CONTROL(PORT_BASE, PIN_MASK) do { REG((PORT_BASE) + GPIO_AFSEL) &= ~(PIN_MASK); } while(0) |
Configure the pin to be software controlled with PIN_MASK of port with PORT_BASE. More... | |
#define | GPIO_POWER_UP_ON_RISING(PORT, PIN_MASK) |
Set pins with PIN_MASK of port PORT to trigger a power-up interrupt on rising edge. More... | |
#define | GPIO_POWER_UP_ON_FALLING(PORT, PIN_MASK) |
Set pins with PIN_MASK of port PORT to trigger a power-up interrupt on falling edge. More... | |
#define | GPIO_ENABLE_POWER_UP_INTERRUPT(PORT, PIN_MASK) |
Enable power-up interrupt triggering for pins with PIN_MASK of port PORT. More... | |
#define | GPIO_DISABLE_POWER_UP_INTERRUPT(PORT, PIN_MASK) |
Disable power-up interrupt triggering for pins with PIN_MASK of port PORT. More... | |
#define | GPIO_GET_POWER_UP_INT_STATUS(PORT) ((REG(GPIO_PORT_TO_BASE(PORT) + GPIO_IRQ_DETECT_ACK) >> ((PORT) << 3)) & 0xFF) |
Get power-up interrupt status of port PORT. More... | |
#define | GPIO_CLEAR_POWER_UP_INTERRUPT(PORT, PIN_MASK) |
Clear power-up interrupt triggering for pins with PIN_MASK of port PORT. More... | |
#define | GPIO_PIN_MASK(PIN) (1 << (PIN)) |
Converts a pin number to a pin mask. More... | |
#define | GPIO_PORT_TO_BASE(PORT) (GPIO_A_BASE + ((PORT) << 12)) |
Converts a port number to the port base address. More... | |
#define | GPIO_PORT_PIN_TO_GPIO_HAL_PIN(PORT, PIN) (((PORT) << 3) + (PIN)) |
Converts a port/pin pair to GPIO HAL pin number. More... | |
GPIO Register offset declarations | |
#define | GPIO_DATA 0x00000000 |
Data register. | |
#define | GPIO_DIR 0x00000400 |
Data direction register. | |
#define | GPIO_IS 0x00000404 |
Interrupt sense. | |
#define | GPIO_IBE 0x00000408 |
Interrupt both edges. | |
#define | GPIO_IEV 0x0000040C |
Interrupt event. | |
#define | GPIO_IE 0x00000410 |
Interrupt mask. | |
#define | GPIO_RIS 0x00000414 |
Interrupt status - raw. | |
#define | GPIO_MIS 0x00000418 |
Interrupt status - masked. | |
#define | GPIO_IC 0x0000041C |
Interrupt clear. | |
#define | GPIO_AFSEL 0x00000420 |
Mode control select. | |
#define | GPIO_GPIOLOCK 0x00000520 |
GPIO commit unlock. | |
#define | GPIO_GPIOCR 0x00000524 |
GPIO commit. | |
#define | GPIO_PMUX 0x00000700 |
PMUX register. | |
#define | GPIO_P_EDGE_CTRL 0x00000704 |
Port edge control. | |
#define | GPIO_USB_CTRL 0x00000708 |
USB input power-up edge ctrl. | |
#define | GPIO_PI_IEN 0x00000710 |
Power-up interrupt enable. | |
#define | GPIO_IRQ_DETECT_ACK 0x00000718 |
IRQ detect ACK - I/O ports. | |
#define | GPIO_USB_IRQ_ACK 0x0000071C |
IRQ detect ACK - USB. | |
#define | GPIO_IRQ_DETECT_UNMASK 0x00000720 |
IRQ detect ACK - masked. | |
GPIO_DATA register bit masks | |
#define | GPIO_DATA_DATA 0x000000FF |
Input and output data. | |
GPIO_DIR register bit masks | |
#define | GPIO_DIR_DIR 0x000000FF |
Pin Input (0) / Output (1) | |
GPIO_IS register bit masks | |
#define | GPIO_IS_IS 0x000000FF |
Detect Edge (0) / Level (1) | |
GPIO_IBE register bit masks | |
#define | GPIO_IBE_IBE 0x000000FF |
Both Edges (1) / Single (0) | |
GPIO_IEV register bit masks | |
#define | GPIO_IEV_IEV 0x000000FF |
Rising (1) / Falling (0) | |
GPIO_IE register bit masks | |
#define | GPIO_IE_IE 0x000000FF |
Masked (0) / Not Masked (1) | |
GPIO_RIS register bit masks | |
#define | GPIO_RIS_RIS 0x000000FF |
Raw interrupt status. | |
GPIO_MIS register bit masks | |
#define | GPIO_MIS_MIS 0x000000FF |
Masked interrupt status. | |
GPIO_IC register bit masks | |
#define | GPIO_IC_IC 0x000000FF |
Clear edge detection (1) | |
GPIO_AFSEL register bit masks | |
#define | GPIO_AFSEL_AFSEL 0x000000FF |
Software (0) / Peripheral (1) | |
GPIO_GPIOLOCK register bit masks | |
#define | GPIO_GPIOLOCK_LOCK 0xFFFFFFFF |
Locked (1) / Unlocked (0) | |
GPIO_GPIOCR register bit masks | |
#define | GPIO_GPIOCR_CR 0x000000FF |
Allow alternate function (1) | |
GPIO_PMUX register bit masks | |
#define | GPIO_PMUX_CKOEN 0x00000080 |
Clock out enable. | |
#define | GPIO_PMUX_CKOPIN 0x00000010 |
Decouple control pin select. | |
#define | GPIO_PMUX_DCEN 0x00000008 |
Decouple control enable. | |
#define | GPIO_PMUX_DCPIN 0x00000001 |
Decouple control pin select. | |
GPIO_P_EDGE_CTRL register bit masks. | |
#define | GPIO_P_EDGE_CTRL_PDIRC7 0x80000000 |
Port D bit 7. | |
#define | GPIO_P_EDGE_CTRL_PDIRC6 0x40000000 |
Port D bit 6. | |
#define | GPIO_P_EDGE_CTRL_PDIRC5 0x20000000 |
Port D bit 5. | |
#define | GPIO_P_EDGE_CTRL_PDIRC4 0x10000000 |
Port D bit 4. | |
#define | GPIO_P_EDGE_CTRL_PDIRC3 0x08000000 |
Port D bit 3. | |
#define | GPIO_P_EDGE_CTRL_PDIRC2 0x04000000 |
Port D bit 2. | |
#define | GPIO_P_EDGE_CTRL_PDIRC1 0x02000000 |
Port D bit 1. | |
#define | GPIO_P_EDGE_CTRL_PDIRC0 0x01000000 |
Port D bit 0. | |
#define | GPIO_P_EDGE_CTRL_PCIRC7 0x00800000 |
Port C bit 7. | |
#define | GPIO_P_EDGE_CTRL_PCIRC6 0x00400000 |
Port C bit 6. | |
#define | GPIO_P_EDGE_CTRL_PCIRC5 0x00200000 |
Port C bit 5. | |
#define | GPIO_P_EDGE_CTRL_PCIRC4 0x00100000 |
Port C bit 4. | |
#define | GPIO_P_EDGE_CTRL_PCIRC3 0x00080000 |
Port C bit 3. | |
#define | GPIO_P_EDGE_CTRL_PCIRC2 0x00040000 |
Port C bit 2. | |
#define | GPIO_P_EDGE_CTRL_PCIRC1 0x00020000 |
Port C bit 1. | |
#define | GPIO_P_EDGE_CTRL_PCIRC0 0x00010000 |
Port C bit 0. | |
#define | GPIO_P_EDGE_CTRL_PBIRC7 0x00008000 |
Port B bit 7. | |
#define | GPIO_P_EDGE_CTRL_PBIRC6 0x00004000 |
Port B bit 6. | |
#define | GPIO_P_EDGE_CTRL_PBIRC5 0x00002000 |
Port B bit 5. | |
#define | GPIO_P_EDGE_CTRL_PBIRC4 0x00001000 |
Port B bit 4. | |
#define | GPIO_P_EDGE_CTRL_PBIRC3 0x00000800 |
Port B bit 3. | |
#define | GPIO_P_EDGE_CTRL_PBIRC2 0x00000400 |
Port B bit 2. | |
#define | GPIO_P_EDGE_CTRL_PBIRC1 0x00000200 |
Port B bit 1. | |
#define | GPIO_P_EDGE_CTRL_PBIRC0 0x00000100 |
Port B bit 0. | |
#define | GPIO_P_EDGE_CTRL_PAIRC7 0x00000080 |
Port A bit 7. | |
#define | GPIO_P_EDGE_CTRL_PAIRC6 0x00000040 |
Port A bit 6. | |
#define | GPIO_P_EDGE_CTRL_PAIRC5 0x00000020 |
Port A bit 5. | |
#define | GPIO_P_EDGE_CTRL_PAIRC4 0x00000010 |
Port A bit 4. | |
#define | GPIO_P_EDGE_CTRL_PAIRC3 0x00000008 |
Port A bit 3. | |
#define | GPIO_P_EDGE_CTRL_PAIRC2 0x00000004 |
Port A bit 2. | |
#define | GPIO_P_EDGE_CTRL_PAIRC1 0x00000002 |
Port A bit 1. | |
#define | GPIO_P_EDGE_CTRL_PAIRC0 0x00000001 |
Port A bit 0. | |
GPIO_USB_CTRL register bit masks | |
#define | GPIO_USB_CTRL_USB_EDGE_CTL 0x00000001 |
Rising (0) / Falling (1) | |
GPIO_PI_IEN register bit masks. | |
#define | GPIO_PI_IEN_PDIEN7 0x80000000 |
Port D bit 7. | |
#define | GPIO_PI_IEN_PDIEN6 0x40000000 |
Port D bit 6. | |
#define | GPIO_PI_IEN_PDIEN5 0x20000000 |
Port D bit 5. | |
#define | GPIO_PI_IEN_PDIEN4 0x10000000 |
Port D bit 4. | |
#define | GPIO_PI_IEN_PDIEN3 0x08000000 |
Port D bit 3. | |
#define | GPIO_PI_IEN_PDIEN2 0x04000000 |
Port D bit 2. | |
#define | GPIO_PI_IEN_PDIEN1 0x02000000 |
Port D bit 1. | |
#define | GPIO_PI_IEN_PDIEN0 0x01000000 |
Port D bit 0. | |
#define | GPIO_PI_IEN_PCIEN7 0x00800000 |
Port C bit 7. | |
#define | GPIO_PI_IEN_PCIEN6 0x00400000 |
Port C bit 6. | |
#define | GPIO_PI_IEN_PCIEN5 0x00200000 |
Port C bit 5. | |
#define | GPIO_PI_IEN_PCIEN4 0x00100000 |
Port C bit 4. | |
#define | GPIO_PI_IEN_PCIEN3 0x00080000 |
Port C bit 3. | |
#define | GPIO_PI_IEN_PCIEN2 0x00040000 |
Port C bit 2. | |
#define | GPIO_PI_IEN_PCIEN1 0x00020000 |
Port C bit 1. | |
#define | GPIO_PI_IEN_PCIEN0 0x00010000 |
Port C bit 0. | |
#define | GPIO_PI_IEN_PBIEN7 0x00008000 |
Port B bit 7. | |
#define | GPIO_PI_IEN_PBIEN6 0x00004000 |
Port B bit 6. | |
#define | GPIO_PI_IEN_PBIEN5 0x00002000 |
Port B bit 5. | |
#define | GPIO_PI_IEN_PBIEN4 0x00001000 |
Port B bit 4. | |
#define | GPIO_PI_IEN_PBIEN3 0x00000800 |
Port B bit 3. | |
#define | GPIO_PI_IEN_PBIEN2 0x00000400 |
Port B bit 2. | |
#define | GPIO_PI_IEN_PBIEN1 0x00000200 |
Port B bit 1. | |
#define | GPIO_PI_IEN_PBIEN0 0x00000100 |
Port B bit 0. | |
#define | GPIO_PI_IEN_PAIEN7 0x00000080 |
Port A bit 7. | |
#define | GPIO_PI_IEN_PAIEN6 0x00000040 |
Port A bit 6. | |
#define | GPIO_PI_IEN_PAIEN5 0x00000020 |
Port A bit 5. | |
#define | GPIO_PI_IEN_PAIEN4 0x00000010 |
Port A bit 4. | |
#define | GPIO_PI_IEN_PAIEN3 0x00000008 |
Port A bit 3. | |
#define | GPIO_PI_IEN_PAIEN2 0x00000004 |
Port A bit 2. | |
#define | GPIO_PI_IEN_PAIEN1 0x00000002 |
Port A bit 1. | |
#define | GPIO_PI_IEN_PAIEN0 0x00000001 |
Port A bit 0. | |
GPIO_IRQ_DETECT_ACK register bit masks | |
#define | GPIO_IRQ_DETECT_ACK_PDIACK7 0x80000000 |
Port D bit 7. | |
#define | GPIO_IRQ_DETECT_ACK_PDIACK6 0x40000000 |
Port D bit 6. | |
#define | GPIO_IRQ_DETECT_ACK_PDIACK5 0x20000000 |
Port D bit 5. | |
#define | GPIO_IRQ_DETECT_ACK_PDIACK4 0x10000000 |
Port D bit 4. | |
#define | GPIO_IRQ_DETECT_ACK_PDIACK3 0x08000000 |
Port D bit 3. | |
#define | GPIO_IRQ_DETECT_ACK_PDIACK2 0x04000000 |
Port D bit 2. | |
#define | GPIO_IRQ_DETECT_ACK_PDIACK1 0x02000000 |
Port D bit 1. | |
#define | GPIO_IRQ_DETECT_ACK_PDIACK0 0x01000000 |
Port D bit 0. | |
#define | GPIO_IRQ_DETECT_ACK_PCIACK7 0x00800000 |
Port C bit 7. | |
#define | GPIO_IRQ_DETECT_ACK_PCIACK6 0x00400000 |
Port C bit 6. | |
#define | GPIO_IRQ_DETECT_ACK_PCIACK5 0x00200000 |
Port C bit 5. | |
#define | GPIO_IRQ_DETECT_ACK_PCIACK4 0x00100000 |
Port C bit 4. | |
#define | GPIO_IRQ_DETECT_ACK_PCIACK3 0x00080000 |
Port C bit 3. | |
#define | GPIO_IRQ_DETECT_ACK_PCIACK2 0x00040000 |
Port C bit 2. | |
#define | GPIO_IRQ_DETECT_ACK_PCIACK1 0x00020000 |
Port C bit 1. | |
#define | GPIO_IRQ_DETECT_ACK_PCIACK0 0x00010000 |
Port C bit 0. | |
#define | GPIO_IRQ_DETECT_ACK_PBIACK7 0x00008000 |
Port B bit 7. | |
#define | GPIO_IRQ_DETECT_ACK_PBIACK6 0x00004000 |
Port B bit 6. | |
#define | GPIO_IRQ_DETECT_ACK_PBIACK5 0x00002000 |
Port B bit 5. | |
#define | GPIO_IRQ_DETECT_ACK_PBIACK4 0x00001000 |
Port B bit 4. | |
#define | GPIO_IRQ_DETECT_ACK_PBIACK3 0x00000800 |
Port B bit 3. | |
#define | GPIO_IRQ_DETECT_ACK_PBIACK2 0x00000400 |
Port B bit 2. | |
#define | GPIO_IRQ_DETECT_ACK_PBIACK1 0x00000200 |
Port B bit 1. | |
#define | GPIO_IRQ_DETECT_ACK_PBIACK0 0x00000100 |
Port B bit 0. | |
#define | GPIO_IRQ_DETECT_ACK_PAIACK7 0x00000080 |
Port A bit 7. | |
#define | GPIO_IRQ_DETECT_ACK_PAIACK6 0x00000040 |
Port A bit 6. | |
#define | GPIO_IRQ_DETECT_ACK_PAIACK5 0x00000020 |
Port A bit 5. | |
#define | GPIO_IRQ_DETECT_ACK_PAIACK4 0x00000010 |
Port A bit 4. | |
#define | GPIO_IRQ_DETECT_ACK_PAIACK3 0x00000008 |
Port A bit 3. | |
#define | GPIO_IRQ_DETECT_ACK_PAIACK2 0x00000004 |
Port A bit 2. | |
#define | GPIO_IRQ_DETECT_ACK_PAIACK1 0x00000002 |
Port A bit 1. | |
#define | GPIO_IRQ_DETECT_ACK_PAIACK0 0x00000001 |
Port A bit 0. | |
GPIO_USB_IRQ_ACK register bit masks | |
#define | GPIO_USB_IRQ_ACK_USBACK 0x00000001 |
Detected (1) / Not detected (0) | |
GPIO_IRQ_DETECT_UNMASK register bit masks. | |
#define | GPIO_IRQ_DETECT_UNMASK_PDIACK7 0x80000000 |
Port D bit 7. | |
#define | GPIO_IRQ_DETECT_UNMASK_PDIACK6 0x40000000 |
Port D bit 6. | |
#define | GPIO_IRQ_DETECT_UNMASK_PDIACK5 0x20000000 |
Port D bit 5. | |
#define | GPIO_IRQ_DETECT_UNMASK_PDIACK4 0x10000000 |
Port D bit 4. | |
#define | GPIO_IRQ_DETECT_UNMASK_PDIACK3 0x08000000 |
Port D bit 3. | |
#define | GPIO_IRQ_DETECT_UNMASK_PDIACK2 0x04000000 |
Port D bit 2. | |
#define | GPIO_IRQ_DETECT_UNMASK_PDIACK1 0x02000000 |
Port D bit 1. | |
#define | GPIO_IRQ_DETECT_UNMASK_PDIACK0 0x01000000 |
Port D bit 0. | |
#define | GPIO_IRQ_DETECT_UNMASK_PCIACK7 0x00800000 |
Port C bit 7. | |
#define | GPIO_IRQ_DETECT_UNMASK_PCIACK6 0x00400000 |
Port C bit 6. | |
#define | GPIO_IRQ_DETECT_UNMASK_PCIACK5 0x00200000 |
Port C bit 5. | |
#define | GPIO_IRQ_DETECT_UNMASK_PCIACK4 0x00100000 |
Port C bit 4. | |
#define | GPIO_IRQ_DETECT_UNMASK_PCIACK3 0x00080000 |
Port C bit 3. | |
#define | GPIO_IRQ_DETECT_UNMASK_PCIACK2 0x00040000 |
Port C bit 2. | |
#define | GPIO_IRQ_DETECT_UNMASK_PCIACK1 0x00020000 |
Port C bit 1. | |
#define | GPIO_IRQ_DETECT_UNMASK_PCIACK0 0x00010000 |
Port C bit 0. | |
#define | GPIO_IRQ_DETECT_UNMASK_PBIACK7 0x00008000 |
Port B bit 7. | |
#define | GPIO_IRQ_DETECT_UNMASK_PBIACK6 0x00004000 |
Port B bit 6. | |
#define | GPIO_IRQ_DETECT_UNMASK_PBIACK5 0x00002000 |
Port B bit 5. | |
#define | GPIO_IRQ_DETECT_UNMASK_PBIACK4 0x00001000 |
Port B bit 4. | |
#define | GPIO_IRQ_DETECT_UNMASK_PBIACK3 0x00000800 |
Port B bit 3. | |
#define | GPIO_IRQ_DETECT_UNMASK_PBIACK2 0x00000400 |
Port B bit 2. | |
#define | GPIO_IRQ_DETECT_UNMASK_PBIACK1 0x00000200 |
Port B bit 1. | |
#define | GPIO_IRQ_DETECT_UNMASK_PBIACK0 0x00000100 |
Port B bit 0. | |
#define | GPIO_IRQ_DETECT_UNMASK_PAIACK7 0x00000080 |
Port A bit 7. | |
#define | GPIO_IRQ_DETECT_UNMASK_PAIACK6 0x00000040 |
Port A bit 6. | |
#define | GPIO_IRQ_DETECT_UNMASK_PAIACK5 0x00000020 |
Port A bit 5. | |
#define | GPIO_IRQ_DETECT_UNMASK_PAIACK4 0x00000010 |
Port A bit 4. | |
#define | GPIO_IRQ_DETECT_UNMASK_PAIACK3 0x00000008 |
Port A bit 3. | |
#define | GPIO_IRQ_DETECT_UNMASK_PAIACK2 0x00000004 |
Port A bit 2. | |
#define | GPIO_IRQ_DETECT_UNMASK_PAIACK1 0x00000002 |
Port A bit 1. | |
#define | GPIO_IRQ_DETECT_UNMASK_PAIACK0 0x00000001 |
Port A bit 0. | |
Driver for the cc2538 GPIO controller.
#define GPIO_CLEAR_INTERRUPT | ( | PORT_BASE, | |
PIN_MASK | |||
) | do { REG((PORT_BASE) + GPIO_IC) = (PIN_MASK); } while(0) |
#define GPIO_CLEAR_POWER_UP_INTERRUPT | ( | PORT, | |
PIN_MASK | |||
) |
Clear power-up interrupt triggering for pins with PIN_MASK of port PORT.
PORT | GPIO Port (not port base address) |
PIN_MASK | Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80 |
#define GPIO_CLR_PIN | ( | PORT_BASE, | |
PIN_MASK | |||
) | do { REG((PORT_BASE) + GPIO_DATA + ((PIN_MASK) << 2)) = 0x00; } while(0) |
Set pins with PIN_MASK of port with PORT_BASE low.
PORT_BASE | GPIO Port register offset |
PIN_MASK | Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80 |
Definition at line 113 of file gpio.h.
Referenced by gpio_hal_arch_no_port_clear_pins().
#define GPIO_DETECT_EDGE | ( | PORT_BASE, | |
PIN_MASK | |||
) | do { REG((PORT_BASE) + GPIO_IS) &= ~(PIN_MASK); } while(0) |
#define GPIO_DETECT_FALLING | ( | PORT_BASE, | |
PIN_MASK | |||
) | do { REG((PORT_BASE) + GPIO_IEV) &= ~(PIN_MASK); } while(0) |
#define GPIO_DETECT_LEVEL | ( | PORT_BASE, | |
PIN_MASK | |||
) | do { REG((PORT_BASE) + GPIO_IS) |= (PIN_MASK); } while(0) |
#define GPIO_DETECT_RISING | ( | PORT_BASE, | |
PIN_MASK | |||
) | do { REG((PORT_BASE) + GPIO_IEV) |= (PIN_MASK); } while(0) |
#define GPIO_DISABLE_INTERRUPT | ( | PORT_BASE, | |
PIN_MASK | |||
) | do { REG((PORT_BASE) + GPIO_IE) &= ~(PIN_MASK); } while(0) |
#define GPIO_DISABLE_POWER_UP_INTERRUPT | ( | PORT, | |
PIN_MASK | |||
) |
Disable power-up interrupt triggering for pins with PIN_MASK of port PORT.
PORT | GPIO Port (not port base address) |
PIN_MASK | Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80 |
#define GPIO_ENABLE_INTERRUPT | ( | PORT_BASE, | |
PIN_MASK | |||
) | do { REG((PORT_BASE) + GPIO_IE) |= (PIN_MASK); } while(0) |
#define GPIO_ENABLE_POWER_UP_INTERRUPT | ( | PORT, | |
PIN_MASK | |||
) |
Enable power-up interrupt triggering for pins with PIN_MASK of port PORT.
PORT | GPIO Port (not port base address) |
PIN_MASK | Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80 |
#define GPIO_GET_MASKED_INT_STATUS | ( | PORT_BASE | ) | REG((PORT_BASE) + GPIO_MIS) |
Get masked interrupt status of port with PORT_BASE.
PORT_BASE | GPIO Port register offset |
The bits set in the returned bit-mask reflect the status of input lines triggering an interrupt. The bits cleared indicate that either no interrupt has been generated, or the interrupt is masked. This is the state of the interrupt after interrupt masking.
#define GPIO_GET_POWER_UP_INT_STATUS | ( | PORT | ) | ((REG(GPIO_PORT_TO_BASE(PORT) + GPIO_IRQ_DETECT_ACK) >> ((PORT) << 3)) & 0xFF) |
#define GPIO_GET_RAW_INT_STATUS | ( | PORT_BASE | ) | REG((PORT_BASE) + GPIO_RIS) |
Get raw interrupt status of port with PORT_BASE.
PORT_BASE | GPIO Port register offset |
The bits set in the returned bit-mask reflect the status of the interrupts trigger conditions detected (raw, before interrupt masking), indicating that all the requirements are met, before they are finally allowed to trigger by the interrupt mask. The bits cleared indicate that corresponding input pins have not initiated an interrupt.
#define GPIO_IS_OUTPUT | ( | PORT_BASE, | |
PIN_MASK | |||
) | (REG((PORT_BASE) + GPIO_DIR) & (PIN_MASK)) |
Return whether pins with PIN_MASK of port with PORT_BASE are set to output.
PORT_BASE | GPIO Port register offset |
PIN_MASK | Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80 |
This macro will not return 0 or 1. Instead, it will return the directions of the pins specified by PIN_MASK ORed together. Thus, if 0xC3 (0x80 | 0x40 | 0x02 | 0x01) is passed as the PIN_MASK and pins 7 and 0 are set to output, the macro will return 0x81.
#define GPIO_PERIPHERAL_CONTROL | ( | PORT_BASE, | |
PIN_MASK | |||
) | do { REG((PORT_BASE) + GPIO_AFSEL) |= (PIN_MASK); } while(0) |
#define GPIO_PIN_MASK | ( | PIN | ) | (1 << (PIN)) |
Converts a pin number to a pin mask.
PIN | The pin number in the range [0..7] |
Definition at line 320 of file gpio.h.
Referenced by spix_cs_init().
#define GPIO_PORT_PIN_TO_GPIO_HAL_PIN | ( | PORT, | |
PIN | |||
) | (((PORT) << 3) + (PIN)) |
#define GPIO_PORT_TO_BASE | ( | PORT | ) | (GPIO_A_BASE + ((PORT) << 12)) |
Converts a port number to the port base address.
PORT | The port number in the range 0 - 3. Likely GPIO_X_NUM. |
Definition at line 328 of file gpio.h.
Referenced by spix_cs_init().
#define GPIO_POWER_UP_ON_FALLING | ( | PORT, | |
PIN_MASK | |||
) |
Set pins with PIN_MASK of port PORT to trigger a power-up interrupt on falling edge.
PORT | GPIO Port (not port base address) |
PIN_MASK | Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80 |
#define GPIO_POWER_UP_ON_RISING | ( | PORT, | |
PIN_MASK | |||
) |
Set pins with PIN_MASK of port PORT to trigger a power-up interrupt on rising edge.
PORT | GPIO Port (not port base address) |
PIN_MASK | Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80 |
#define GPIO_READ_PIN | ( | PORT_BASE, | |
PIN_MASK | |||
) | REG((PORT_BASE) + GPIO_DATA + ((PIN_MASK) << 2)) |
Read pins with PIN_MASK of port with PORT_BASE.
PORT_BASE | GPIO Port register offset |
PIN_MASK | Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80 |
This macro will not return 0 or 1. Instead, it will return the values of the pins specified by PIN_MASK ORd together. Thus, if you pass 0xC3 (0x80 | 0x40 | 0x02 | 0x01) as the PIN_MASK and pins 7 and 0 are high, the macro will return 0x81.
Definition at line 147 of file gpio.h.
Referenced by gpio_hal_arch_no_port_read_pins().
#define GPIO_SET_INPUT | ( | PORT_BASE, | |
PIN_MASK | |||
) | do { REG((PORT_BASE) + GPIO_DIR) &= ~(PIN_MASK); } while(0) |
#define GPIO_SET_OUTPUT | ( | PORT_BASE, | |
PIN_MASK | |||
) | do { REG((PORT_BASE) + GPIO_DIR) |= (PIN_MASK); } while(0) |
Set pins with PIN_MASK of port with PORT_BASE to output.
PORT_BASE | GPIO Port register offset |
PIN_MASK | Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80 |
Definition at line 85 of file gpio.h.
Referenced by antenna_init(), spix_cs_init(), and tps62730_init().
#define GPIO_SET_PIN | ( | PORT_BASE, | |
PIN_MASK | |||
) | do { REG((PORT_BASE) + GPIO_DATA + ((PIN_MASK) << 2)) = 0xFF; } while(0) |
Set pins with PIN_MASK of port with PORT_BASE high.
PORT_BASE | GPIO Port register offset |
PIN_MASK | Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80 |
Definition at line 106 of file gpio.h.
Referenced by gpio_hal_arch_no_port_set_pins(), and spix_cs_init().
#define GPIO_SOFTWARE_CONTROL | ( | PORT_BASE, | |
PIN_MASK | |||
) | do { REG((PORT_BASE) + GPIO_AFSEL) &= ~(PIN_MASK); } while(0) |
Configure the pin to be software controlled with PIN_MASK of port with PORT_BASE.
PORT_BASE | GPIO Port register offset |
PIN_MASK | Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80 |
Definition at line 258 of file gpio.h.
Referenced by antenna_sw_config(), led_strip_config(), pm_enable(), pm_init(), and spix_cs_init().
#define GPIO_TRIGGER_BOTH_EDGES | ( | PORT_BASE, | |
PIN_MASK | |||
) | do { REG((PORT_BASE) + GPIO_IBE) |= (PIN_MASK); } while(0) |
#define GPIO_TRIGGER_SINGLE_EDGE | ( | PORT_BASE, | |
PIN_MASK | |||
) | do { REG((PORT_BASE) + GPIO_IBE) &= ~(PIN_MASK); } while(0) |
#define GPIO_WRITE_PIN | ( | PORT_BASE, | |
PIN_MASK, | |||
value | |||
) | do { REG((PORT_BASE) + GPIO_DATA + ((PIN_MASK) << 2)) = (value); } while(0) |
Set pins with PIN_MASK of port with PORT_BASE to value.
PORT_BASE | GPIO Port register offset |
PIN_MASK | Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80 |
value | The new value to write to the register. Only pins specified by PIN_MASK will be set. |
Thus, if you only want to set a single pin (e.g. pin 2), do not pass 1, but you must pass 0x04 instead (1 << 2). This may seem counter-intuitive at first glance, but it allows a single invocation of this macro to set multiple pins in one go if so desired. For example, you can set pins 3 and 1 and the same time clear pins 2 and 0. To do so, pass 0x0F as the PIN_MASK and then use 0x0A as the value ((1 << 3) | (1 << 1) for pins 3 and 1)
Definition at line 134 of file gpio.h.
Referenced by antenna_external(), and antenna_internal().
|
static |
Interrupt service routine for Port port.
port | Number between 0 and 3. Port A: 0, Port B: 1, etc. |
Definition at line 52 of file gpio.c.
References int_status().