35 #if defined ( __ICCARM__ ) 36 #pragma system_include 37 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 38 #pragma clang system_header 41 #ifndef __CORE_CM4_H_GENERIC 42 #define __CORE_CM4_H_GENERIC 74 #define __CM4_CMSIS_VERSION_MAIN (0x04U) 75 #define __CM4_CMSIS_VERSION_SUB (0x1EU) 76 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ 77 __CM4_CMSIS_VERSION_SUB ) 79 #define __CORTEX_M (0x04U) 82 #if defined ( __CC_ARM ) 84 #define __INLINE __inline 85 #define __STATIC_INLINE static __inline 87 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 89 #define __INLINE __inline 90 #define __STATIC_INLINE static __inline 92 #elif defined ( __GNUC__ ) 94 #define __INLINE inline 95 #define __STATIC_INLINE static inline 97 #elif defined ( __ICCARM__ ) 99 #define __INLINE inline 100 #define __STATIC_INLINE static inline 102 #elif defined ( __TMS470__ ) 104 #define __STATIC_INLINE static inline 106 #elif defined ( __TASKING__ ) 108 #define __INLINE inline 109 #define __STATIC_INLINE static inline 111 #elif defined ( __CSMC__ ) 114 #define __INLINE inline 115 #define __STATIC_INLINE static inline 118 #error Unknown compiler 124 #if defined ( __CC_ARM ) 125 #if defined __TARGET_FPU_VFP 126 #if (__FPU_PRESENT == 1U) 127 #define __FPU_USED 1U 129 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 130 #define __FPU_USED 0U 133 #define __FPU_USED 0U 136 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 137 #if defined __ARM_PCS_VFP 138 #if (__FPU_PRESENT == 1) 139 #define __FPU_USED 1U 141 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 142 #define __FPU_USED 0U 145 #define __FPU_USED 0U 148 #elif defined ( __GNUC__ ) 149 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 150 #if (__FPU_PRESENT == 1U) 151 #define __FPU_USED 1U 153 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 154 #define __FPU_USED 0U 157 #define __FPU_USED 0U 160 #elif defined ( __ICCARM__ ) 161 #if defined __ARMVFP__ 162 #if (__FPU_PRESENT == 1U) 163 #define __FPU_USED 1U 165 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 166 #define __FPU_USED 0U 169 #define __FPU_USED 0U 172 #elif defined ( __TMS470__ ) 173 #if defined __TI_VFP_SUPPORT__ 174 #if (__FPU_PRESENT == 1U) 175 #define __FPU_USED 1U 177 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 178 #define __FPU_USED 0U 181 #define __FPU_USED 0U 184 #elif defined ( __TASKING__ ) 185 #if defined __FPU_VFP__ 186 #if (__FPU_PRESENT == 1U) 187 #define __FPU_USED 1U 189 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 190 #define __FPU_USED 0U 193 #define __FPU_USED 0U 196 #elif defined ( __CSMC__ ) 197 #if ( __CSMC__ & 0x400U) 198 #if (__FPU_PRESENT == 1U) 199 #define __FPU_USED 1U 201 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 202 #define __FPU_USED 0U 205 #define __FPU_USED 0U 220 #ifndef __CMSIS_GENERIC 222 #ifndef __CORE_CM4_H_DEPENDANT 223 #define __CORE_CM4_H_DEPENDANT 230 #if defined __CHECK_DEVICE_DEFINES 232 #define __CM4_REV 0x0000U 233 #warning "__CM4_REV not defined in device header file; using default!" 236 #ifndef __FPU_PRESENT 237 #define __FPU_PRESENT 0U 238 #warning "__FPU_PRESENT not defined in device header file; using default!" 241 #ifndef __MPU_PRESENT 242 #define __MPU_PRESENT 0U 243 #warning "__MPU_PRESENT not defined in device header file; using default!" 246 #ifndef __NVIC_PRIO_BITS 247 #define __NVIC_PRIO_BITS 4U 248 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 251 #ifndef __Vendor_SysTickConfig 252 #define __Vendor_SysTickConfig 0U 253 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 268 #define __I volatile const 271 #define __IO volatile 274 #define __IM volatile const 275 #define __OM volatile 276 #define __IOM volatile 312 uint32_t _reserved0:16;
325 #define APSR_N_Pos 31U 326 #define APSR_N_Msk (1UL << APSR_N_Pos) 328 #define APSR_Z_Pos 30U 329 #define APSR_Z_Msk (1UL << APSR_Z_Pos) 331 #define APSR_C_Pos 29U 332 #define APSR_C_Msk (1UL << APSR_C_Pos) 334 #define APSR_V_Pos 28U 335 #define APSR_V_Msk (1UL << APSR_V_Pos) 337 #define APSR_Q_Pos 27U 338 #define APSR_Q_Msk (1UL << APSR_Q_Pos) 340 #define APSR_GE_Pos 16U 341 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) 352 uint32_t _reserved0:23;
358 #define IPSR_ISR_Pos 0U 359 #define IPSR_ISR_Msk (0x1FFUL ) 370 uint32_t _reserved0:7;
372 uint32_t _reserved1:4;
385 #define xPSR_N_Pos 31U 386 #define xPSR_N_Msk (1UL << xPSR_N_Pos) 388 #define xPSR_Z_Pos 30U 389 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) 391 #define xPSR_C_Pos 29U 392 #define xPSR_C_Msk (1UL << xPSR_C_Pos) 394 #define xPSR_V_Pos 28U 395 #define xPSR_V_Msk (1UL << xPSR_V_Pos) 397 #define xPSR_Q_Pos 27U 398 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) 400 #define xPSR_IT_Pos 25U 401 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) 403 #define xPSR_T_Pos 24U 404 #define xPSR_T_Msk (1UL << xPSR_T_Pos) 406 #define xPSR_GE_Pos 16U 407 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) 409 #define xPSR_ISR_Pos 0U 410 #define xPSR_ISR_Msk (0x1FFUL ) 423 uint32_t _reserved0:29;
429 #define CONTROL_FPCA_Pos 2U 430 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) 432 #define CONTROL_SPSEL_Pos 1U 433 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) 435 #define CONTROL_nPRIV_Pos 0U 436 #define CONTROL_nPRIV_Msk (1UL ) 453 __IOM uint32_t ISER[8U];
454 uint32_t RESERVED0[24U];
455 __IOM uint32_t ICER[8U];
456 uint32_t RSERVED1[24U];
457 __IOM uint32_t ISPR[8U];
458 uint32_t RESERVED2[24U];
459 __IOM uint32_t ICPR[8U];
460 uint32_t RESERVED3[24U];
461 __IOM uint32_t IABR[8U];
462 uint32_t RESERVED4[56U];
463 __IOM uint8_t IP[240U];
464 uint32_t RESERVED5[644U];
469 #define NVIC_STIR_INTID_Pos 0U 470 #define NVIC_STIR_INTID_Msk (0x1FFUL ) 490 __IOM uint32_t AIRCR;
493 __IOM uint8_t SHP[12U];
494 __IOM uint32_t SHCSR;
498 __IOM uint32_t MMFAR;
501 __IM uint32_t PFR[2U];
504 __IM uint32_t MMFR[4U];
505 __IM uint32_t ISAR[5U];
506 uint32_t RESERVED0[5U];
507 __IOM uint32_t CPACR;
511 #define SCB_CPUID_IMPLEMENTER_Pos 24U 512 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) 514 #define SCB_CPUID_VARIANT_Pos 20U 515 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) 517 #define SCB_CPUID_ARCHITECTURE_Pos 16U 518 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) 520 #define SCB_CPUID_PARTNO_Pos 4U 521 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) 523 #define SCB_CPUID_REVISION_Pos 0U 524 #define SCB_CPUID_REVISION_Msk (0xFUL ) 527 #define SCB_ICSR_NMIPENDSET_Pos 31U 528 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) 530 #define SCB_ICSR_PENDSVSET_Pos 28U 531 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) 533 #define SCB_ICSR_PENDSVCLR_Pos 27U 534 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) 536 #define SCB_ICSR_PENDSTSET_Pos 26U 537 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) 539 #define SCB_ICSR_PENDSTCLR_Pos 25U 540 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) 542 #define SCB_ICSR_ISRPREEMPT_Pos 23U 543 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) 545 #define SCB_ICSR_ISRPENDING_Pos 22U 546 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) 548 #define SCB_ICSR_VECTPENDING_Pos 12U 549 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) 551 #define SCB_ICSR_RETTOBASE_Pos 11U 552 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) 554 #define SCB_ICSR_VECTACTIVE_Pos 0U 555 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL ) 558 #define SCB_VTOR_TBLOFF_Pos 7U 559 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) 562 #define SCB_AIRCR_VECTKEY_Pos 16U 563 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) 565 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U 566 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) 568 #define SCB_AIRCR_ENDIANESS_Pos 15U 569 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) 571 #define SCB_AIRCR_PRIGROUP_Pos 8U 572 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) 574 #define SCB_AIRCR_SYSRESETREQ_Pos 2U 575 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) 577 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U 578 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) 580 #define SCB_AIRCR_VECTRESET_Pos 0U 581 #define SCB_AIRCR_VECTRESET_Msk (1UL ) 584 #define SCB_SCR_SEVONPEND_Pos 4U 585 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) 587 #define SCB_SCR_SLEEPDEEP_Pos 2U 588 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) 590 #define SCB_SCR_SLEEPONEXIT_Pos 1U 591 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) 594 #define SCB_CCR_STKALIGN_Pos 9U 595 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) 597 #define SCB_CCR_BFHFNMIGN_Pos 8U 598 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) 600 #define SCB_CCR_DIV_0_TRP_Pos 4U 601 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) 603 #define SCB_CCR_UNALIGN_TRP_Pos 3U 604 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) 606 #define SCB_CCR_USERSETMPEND_Pos 1U 607 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) 609 #define SCB_CCR_NONBASETHRDENA_Pos 0U 610 #define SCB_CCR_NONBASETHRDENA_Msk (1UL ) 613 #define SCB_SHCSR_USGFAULTENA_Pos 18U 614 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) 616 #define SCB_SHCSR_BUSFAULTENA_Pos 17U 617 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) 619 #define SCB_SHCSR_MEMFAULTENA_Pos 16U 620 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) 622 #define SCB_SHCSR_SVCALLPENDED_Pos 15U 623 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) 625 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U 626 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) 628 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U 629 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) 631 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U 632 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) 634 #define SCB_SHCSR_SYSTICKACT_Pos 11U 635 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) 637 #define SCB_SHCSR_PENDSVACT_Pos 10U 638 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) 640 #define SCB_SHCSR_MONITORACT_Pos 8U 641 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) 643 #define SCB_SHCSR_SVCALLACT_Pos 7U 644 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) 646 #define SCB_SHCSR_USGFAULTACT_Pos 3U 647 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) 649 #define SCB_SHCSR_BUSFAULTACT_Pos 1U 650 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) 652 #define SCB_SHCSR_MEMFAULTACT_Pos 0U 653 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL ) 656 #define SCB_CFSR_USGFAULTSR_Pos 16U 657 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) 659 #define SCB_CFSR_BUSFAULTSR_Pos 8U 660 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) 662 #define SCB_CFSR_MEMFAULTSR_Pos 0U 663 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL ) 666 #define SCB_HFSR_DEBUGEVT_Pos 31U 667 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) 669 #define SCB_HFSR_FORCED_Pos 30U 670 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) 672 #define SCB_HFSR_VECTTBL_Pos 1U 673 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) 676 #define SCB_DFSR_EXTERNAL_Pos 4U 677 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) 679 #define SCB_DFSR_VCATCH_Pos 3U 680 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) 682 #define SCB_DFSR_DWTTRAP_Pos 2U 683 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) 685 #define SCB_DFSR_BKPT_Pos 1U 686 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) 688 #define SCB_DFSR_HALTED_Pos 0U 689 #define SCB_DFSR_HALTED_Msk (1UL ) 706 uint32_t RESERVED0[1U];
708 __IOM uint32_t ACTLR;
712 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U 713 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL ) 716 #define SCnSCB_ACTLR_DISOOFP_Pos 9U 717 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) 719 #define SCnSCB_ACTLR_DISFPCA_Pos 8U 720 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) 722 #define SCnSCB_ACTLR_DISFOLD_Pos 2U 723 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) 725 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U 726 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) 728 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U 729 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL ) 753 #define SysTick_CTRL_COUNTFLAG_Pos 16U 754 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) 756 #define SysTick_CTRL_CLKSOURCE_Pos 2U 757 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) 759 #define SysTick_CTRL_TICKINT_Pos 1U 760 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) 762 #define SysTick_CTRL_ENABLE_Pos 0U 763 #define SysTick_CTRL_ENABLE_Msk (1UL ) 766 #define SysTick_LOAD_RELOAD_Pos 0U 767 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL ) 770 #define SysTick_VAL_CURRENT_Pos 0U 771 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL ) 774 #define SysTick_CALIB_NOREF_Pos 31U 775 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) 777 #define SysTick_CALIB_SKEW_Pos 30U 778 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) 780 #define SysTick_CALIB_TENMS_Pos 0U 781 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL ) 804 uint32_t RESERVED0[864U];
806 uint32_t RESERVED1[15U];
808 uint32_t RESERVED2[15U];
810 uint32_t RESERVED3[29U];
814 uint32_t RESERVED4[43U];
817 uint32_t RESERVED5[6U];
833 #define ITM_TPR_PRIVMASK_Pos 0U 834 #define ITM_TPR_PRIVMASK_Msk (0xFUL ) 837 #define ITM_TCR_BUSY_Pos 23U 838 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) 840 #define ITM_TCR_TraceBusID_Pos 16U 841 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) 843 #define ITM_TCR_GTSFREQ_Pos 10U 844 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) 846 #define ITM_TCR_TSPrescale_Pos 8U 847 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) 849 #define ITM_TCR_SWOENA_Pos 4U 850 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) 852 #define ITM_TCR_DWTENA_Pos 3U 853 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) 855 #define ITM_TCR_SYNCENA_Pos 2U 856 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) 858 #define ITM_TCR_TSENA_Pos 1U 859 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) 861 #define ITM_TCR_ITMENA_Pos 0U 862 #define ITM_TCR_ITMENA_Msk (1UL ) 865 #define ITM_IWR_ATVALIDM_Pos 0U 866 #define ITM_IWR_ATVALIDM_Msk (1UL ) 869 #define ITM_IRR_ATREADYM_Pos 0U 870 #define ITM_IRR_ATREADYM_Msk (1UL ) 873 #define ITM_IMCR_INTEGRATION_Pos 0U 874 #define ITM_IMCR_INTEGRATION_Msk (1UL ) 877 #define ITM_LSR_ByteAcc_Pos 2U 878 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) 880 #define ITM_LSR_Access_Pos 1U 881 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) 883 #define ITM_LSR_Present_Pos 0U 884 #define ITM_LSR_Present_Msk (1UL ) 902 __IOM uint32_t CYCCNT;
903 __IOM uint32_t CPICNT;
904 __IOM uint32_t EXCCNT;
905 __IOM uint32_t SLEEPCNT;
906 __IOM uint32_t LSUCNT;
907 __IOM uint32_t FOLDCNT;
909 __IOM uint32_t COMP0;
910 __IOM uint32_t MASK0;
911 __IOM uint32_t FUNCTION0;
912 uint32_t RESERVED0[1U];
913 __IOM uint32_t COMP1;
914 __IOM uint32_t MASK1;
915 __IOM uint32_t FUNCTION1;
916 uint32_t RESERVED1[1U];
917 __IOM uint32_t COMP2;
918 __IOM uint32_t MASK2;
919 __IOM uint32_t FUNCTION2;
920 uint32_t RESERVED2[1U];
921 __IOM uint32_t COMP3;
922 __IOM uint32_t MASK3;
923 __IOM uint32_t FUNCTION3;
927 #define DWT_CTRL_NUMCOMP_Pos 28U 928 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) 930 #define DWT_CTRL_NOTRCPKT_Pos 27U 931 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) 933 #define DWT_CTRL_NOEXTTRIG_Pos 26U 934 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) 936 #define DWT_CTRL_NOCYCCNT_Pos 25U 937 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) 939 #define DWT_CTRL_NOPRFCNT_Pos 24U 940 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) 942 #define DWT_CTRL_CYCEVTENA_Pos 22U 943 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) 945 #define DWT_CTRL_FOLDEVTENA_Pos 21U 946 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) 948 #define DWT_CTRL_LSUEVTENA_Pos 20U 949 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) 951 #define DWT_CTRL_SLEEPEVTENA_Pos 19U 952 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) 954 #define DWT_CTRL_EXCEVTENA_Pos 18U 955 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) 957 #define DWT_CTRL_CPIEVTENA_Pos 17U 958 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) 960 #define DWT_CTRL_EXCTRCENA_Pos 16U 961 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) 963 #define DWT_CTRL_PCSAMPLENA_Pos 12U 964 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) 966 #define DWT_CTRL_SYNCTAP_Pos 10U 967 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) 969 #define DWT_CTRL_CYCTAP_Pos 9U 970 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) 972 #define DWT_CTRL_POSTINIT_Pos 5U 973 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) 975 #define DWT_CTRL_POSTPRESET_Pos 1U 976 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) 978 #define DWT_CTRL_CYCCNTENA_Pos 0U 979 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL ) 982 #define DWT_CPICNT_CPICNT_Pos 0U 983 #define DWT_CPICNT_CPICNT_Msk (0xFFUL ) 986 #define DWT_EXCCNT_EXCCNT_Pos 0U 987 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL ) 990 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U 991 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL ) 994 #define DWT_LSUCNT_LSUCNT_Pos 0U 995 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL ) 998 #define DWT_FOLDCNT_FOLDCNT_Pos 0U 999 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL ) 1002 #define DWT_MASK_MASK_Pos 0U 1003 #define DWT_MASK_MASK_Msk (0x1FUL ) 1006 #define DWT_FUNCTION_MATCHED_Pos 24U 1007 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) 1009 #define DWT_FUNCTION_DATAVADDR1_Pos 16U 1010 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) 1012 #define DWT_FUNCTION_DATAVADDR0_Pos 12U 1013 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) 1015 #define DWT_FUNCTION_DATAVSIZE_Pos 10U 1016 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) 1018 #define DWT_FUNCTION_LNK1ENA_Pos 9U 1019 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) 1021 #define DWT_FUNCTION_DATAVMATCH_Pos 8U 1022 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) 1024 #define DWT_FUNCTION_CYCMATCH_Pos 7U 1025 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) 1027 #define DWT_FUNCTION_EMITRANGE_Pos 5U 1028 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) 1030 #define DWT_FUNCTION_FUNCTION_Pos 0U 1031 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL ) 1048 __IOM uint32_t SSPSR;
1049 __IOM uint32_t CSPSR;
1050 uint32_t RESERVED0[2U];
1051 __IOM uint32_t ACPR;
1052 uint32_t RESERVED1[55U];
1053 __IOM uint32_t SPPR;
1054 uint32_t RESERVED2[131U];
1056 __IOM uint32_t FFCR;
1058 uint32_t RESERVED3[759U];
1059 __IM uint32_t TRIGGER;
1060 __IM uint32_t FIFO0;
1061 __IM uint32_t ITATBCTR2;
1062 uint32_t RESERVED4[1U];
1063 __IM uint32_t ITATBCTR0;
1064 __IM uint32_t FIFO1;
1065 __IOM uint32_t ITCTRL;
1066 uint32_t RESERVED5[39U];
1067 __IOM uint32_t CLAIMSET;
1068 __IOM uint32_t CLAIMCLR;
1069 uint32_t RESERVED7[8U];
1070 __IM uint32_t DEVID;
1071 __IM uint32_t DEVTYPE;
1075 #define TPI_ACPR_PRESCALER_Pos 0U 1076 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL ) 1079 #define TPI_SPPR_TXMODE_Pos 0U 1080 #define TPI_SPPR_TXMODE_Msk (0x3UL ) 1083 #define TPI_FFSR_FtNonStop_Pos 3U 1084 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) 1086 #define TPI_FFSR_TCPresent_Pos 2U 1087 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) 1089 #define TPI_FFSR_FtStopped_Pos 1U 1090 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) 1092 #define TPI_FFSR_FlInProg_Pos 0U 1093 #define TPI_FFSR_FlInProg_Msk (0x1UL ) 1096 #define TPI_FFCR_TrigIn_Pos 8U 1097 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) 1099 #define TPI_FFCR_EnFCont_Pos 1U 1100 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) 1103 #define TPI_TRIGGER_TRIGGER_Pos 0U 1104 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL ) 1107 #define TPI_FIFO0_ITM_ATVALID_Pos 29U 1108 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) 1110 #define TPI_FIFO0_ITM_bytecount_Pos 27U 1111 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) 1113 #define TPI_FIFO0_ETM_ATVALID_Pos 26U 1114 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) 1116 #define TPI_FIFO0_ETM_bytecount_Pos 24U 1117 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) 1119 #define TPI_FIFO0_ETM2_Pos 16U 1120 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) 1122 #define TPI_FIFO0_ETM1_Pos 8U 1123 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) 1125 #define TPI_FIFO0_ETM0_Pos 0U 1126 #define TPI_FIFO0_ETM0_Msk (0xFFUL ) 1129 #define TPI_ITATBCTR2_ATREADY_Pos 0U 1130 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL ) 1133 #define TPI_FIFO1_ITM_ATVALID_Pos 29U 1134 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) 1136 #define TPI_FIFO1_ITM_bytecount_Pos 27U 1137 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) 1139 #define TPI_FIFO1_ETM_ATVALID_Pos 26U 1140 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) 1142 #define TPI_FIFO1_ETM_bytecount_Pos 24U 1143 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) 1145 #define TPI_FIFO1_ITM2_Pos 16U 1146 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) 1148 #define TPI_FIFO1_ITM1_Pos 8U 1149 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) 1151 #define TPI_FIFO1_ITM0_Pos 0U 1152 #define TPI_FIFO1_ITM0_Msk (0xFFUL ) 1155 #define TPI_ITATBCTR0_ATREADY_Pos 0U 1156 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL ) 1159 #define TPI_ITCTRL_Mode_Pos 0U 1160 #define TPI_ITCTRL_Mode_Msk (0x1UL ) 1163 #define TPI_DEVID_NRZVALID_Pos 11U 1164 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) 1166 #define TPI_DEVID_MANCVALID_Pos 10U 1167 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) 1169 #define TPI_DEVID_PTINVALID_Pos 9U 1170 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) 1172 #define TPI_DEVID_MinBufSz_Pos 6U 1173 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) 1175 #define TPI_DEVID_AsynClkIn_Pos 5U 1176 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) 1178 #define TPI_DEVID_NrTraceInput_Pos 0U 1179 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL ) 1182 #define TPI_DEVTYPE_MajorType_Pos 4U 1183 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) 1185 #define TPI_DEVTYPE_SubType_Pos 0U 1186 #define TPI_DEVTYPE_SubType_Msk (0xFUL ) 1191 #if (__MPU_PRESENT == 1U) 1205 __IOM uint32_t CTRL;
1207 __IOM uint32_t RBAR;
1208 __IOM uint32_t RASR;
1209 __IOM uint32_t RBAR_A1;
1210 __IOM uint32_t RASR_A1;
1211 __IOM uint32_t RBAR_A2;
1212 __IOM uint32_t RASR_A2;
1213 __IOM uint32_t RBAR_A3;
1214 __IOM uint32_t RASR_A3;
1218 #define MPU_TYPE_IREGION_Pos 16U 1219 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) 1221 #define MPU_TYPE_DREGION_Pos 8U 1222 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) 1224 #define MPU_TYPE_SEPARATE_Pos 0U 1225 #define MPU_TYPE_SEPARATE_Msk (1UL ) 1228 #define MPU_CTRL_PRIVDEFENA_Pos 2U 1229 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) 1231 #define MPU_CTRL_HFNMIENA_Pos 1U 1232 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) 1234 #define MPU_CTRL_ENABLE_Pos 0U 1235 #define MPU_CTRL_ENABLE_Msk (1UL ) 1238 #define MPU_RNR_REGION_Pos 0U 1239 #define MPU_RNR_REGION_Msk (0xFFUL ) 1242 #define MPU_RBAR_ADDR_Pos 5U 1243 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) 1245 #define MPU_RBAR_VALID_Pos 4U 1246 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) 1248 #define MPU_RBAR_REGION_Pos 0U 1249 #define MPU_RBAR_REGION_Msk (0xFUL ) 1252 #define MPU_RASR_ATTRS_Pos 16U 1253 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) 1255 #define MPU_RASR_XN_Pos 28U 1256 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) 1258 #define MPU_RASR_AP_Pos 24U 1259 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) 1261 #define MPU_RASR_TEX_Pos 19U 1262 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) 1264 #define MPU_RASR_S_Pos 18U 1265 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) 1267 #define MPU_RASR_C_Pos 17U 1268 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) 1270 #define MPU_RASR_B_Pos 16U 1271 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) 1273 #define MPU_RASR_SRD_Pos 8U 1274 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) 1276 #define MPU_RASR_SIZE_Pos 1U 1277 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) 1279 #define MPU_RASR_ENABLE_Pos 0U 1280 #define MPU_RASR_ENABLE_Msk (1UL ) 1286 #if (__FPU_PRESENT == 1U) 1299 uint32_t RESERVED0[1U];
1300 __IOM uint32_t FPCCR;
1301 __IOM uint32_t FPCAR;
1302 __IOM uint32_t FPDSCR;
1303 __IM uint32_t MVFR0;
1304 __IM uint32_t MVFR1;
1308 #define FPU_FPCCR_ASPEN_Pos 31U 1309 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) 1311 #define FPU_FPCCR_LSPEN_Pos 30U 1312 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) 1314 #define FPU_FPCCR_MONRDY_Pos 8U 1315 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) 1317 #define FPU_FPCCR_BFRDY_Pos 6U 1318 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) 1320 #define FPU_FPCCR_MMRDY_Pos 5U 1321 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) 1323 #define FPU_FPCCR_HFRDY_Pos 4U 1324 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) 1326 #define FPU_FPCCR_THREAD_Pos 3U 1327 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) 1329 #define FPU_FPCCR_USER_Pos 1U 1330 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) 1332 #define FPU_FPCCR_LSPACT_Pos 0U 1333 #define FPU_FPCCR_LSPACT_Msk (1UL ) 1336 #define FPU_FPCAR_ADDRESS_Pos 3U 1337 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) 1340 #define FPU_FPDSCR_AHP_Pos 26U 1341 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) 1343 #define FPU_FPDSCR_DN_Pos 25U 1344 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) 1346 #define FPU_FPDSCR_FZ_Pos 24U 1347 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) 1349 #define FPU_FPDSCR_RMode_Pos 22U 1350 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) 1353 #define FPU_MVFR0_FP_rounding_modes_Pos 28U 1354 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) 1356 #define FPU_MVFR0_Short_vectors_Pos 24U 1357 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) 1359 #define FPU_MVFR0_Square_root_Pos 20U 1360 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) 1362 #define FPU_MVFR0_Divide_Pos 16U 1363 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) 1365 #define FPU_MVFR0_FP_excep_trapping_Pos 12U 1366 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) 1368 #define FPU_MVFR0_Double_precision_Pos 8U 1369 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) 1371 #define FPU_MVFR0_Single_precision_Pos 4U 1372 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) 1374 #define FPU_MVFR0_A_SIMD_registers_Pos 0U 1375 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL ) 1378 #define FPU_MVFR1_FP_fused_MAC_Pos 28U 1379 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) 1381 #define FPU_MVFR1_FP_HPFP_Pos 24U 1382 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) 1384 #define FPU_MVFR1_D_NaN_mode_Pos 4U 1385 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) 1387 #define FPU_MVFR1_FtZ_mode_Pos 0U 1388 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL ) 1406 __IOM uint32_t DHCSR;
1407 __OM uint32_t DCRSR;
1408 __IOM uint32_t DCRDR;
1409 __IOM uint32_t DEMCR;
1413 #define CoreDebug_DHCSR_DBGKEY_Pos 16U 1414 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) 1416 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U 1417 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) 1419 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U 1420 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) 1422 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U 1423 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) 1425 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U 1426 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) 1428 #define CoreDebug_DHCSR_S_HALT_Pos 17U 1429 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) 1431 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U 1432 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) 1434 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U 1435 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) 1437 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U 1438 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) 1440 #define CoreDebug_DHCSR_C_STEP_Pos 2U 1441 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) 1443 #define CoreDebug_DHCSR_C_HALT_Pos 1U 1444 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) 1446 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U 1447 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL ) 1450 #define CoreDebug_DCRSR_REGWnR_Pos 16U 1451 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) 1453 #define CoreDebug_DCRSR_REGSEL_Pos 0U 1454 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL ) 1457 #define CoreDebug_DEMCR_TRCENA_Pos 24U 1458 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) 1460 #define CoreDebug_DEMCR_MON_REQ_Pos 19U 1461 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) 1463 #define CoreDebug_DEMCR_MON_STEP_Pos 18U 1464 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) 1466 #define CoreDebug_DEMCR_MON_PEND_Pos 17U 1467 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) 1469 #define CoreDebug_DEMCR_MON_EN_Pos 16U 1470 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) 1472 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U 1473 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) 1475 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U 1476 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) 1478 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U 1479 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) 1481 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U 1482 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) 1484 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U 1485 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) 1487 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U 1488 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) 1490 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U 1491 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) 1493 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U 1494 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL ) 1512 #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) 1520 #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) 1533 #define SCS_BASE (0xE000E000UL) 1534 #define ITM_BASE (0xE0000000UL) 1535 #define DWT_BASE (0xE0001000UL) 1536 #define TPI_BASE (0xE0040000UL) 1537 #define CoreDebug_BASE (0xE000EDF0UL) 1538 #define SysTick_BASE (SCS_BASE + 0x0010UL) 1539 #define NVIC_BASE (SCS_BASE + 0x0100UL) 1540 #define SCB_BASE (SCS_BASE + 0x0D00UL) 1542 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) 1543 #define SCB ((SCB_Type *) SCB_BASE ) 1544 #define SysTick ((SysTick_Type *) SysTick_BASE ) 1545 #define NVIC ((NVIC_Type *) NVIC_BASE ) 1546 #define ITM ((ITM_Type *) ITM_BASE ) 1547 #define DWT ((DWT_Type *) DWT_BASE ) 1548 #define TPI ((TPI_Type *) TPI_BASE ) 1549 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) 1551 #if (__MPU_PRESENT == 1U) 1552 #define MPU_BASE (SCS_BASE + 0x0D90UL) 1553 #define MPU ((MPU_Type *) MPU_BASE ) 1556 #if (__FPU_PRESENT == 1U) 1557 #define FPU_BASE (SCS_BASE + 0x0F30UL) 1558 #define FPU ((FPU_Type *) FPU_BASE ) 1599 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);
1601 reg_value =
SCB->AIRCR;
1603 reg_value = (reg_value |
1605 (PriorityGroupTmp << 8U) );
1606 SCB->AIRCR = reg_value;
1630 return((uint32_t)(((
NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1641 NVIC->ISER[(((uint32_t)(int32_t)
IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1652 NVIC->ICER[(((uint32_t)(int32_t)
IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1665 return((uint32_t)(((
NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1676 NVIC->ISPR[(((uint32_t)(int32_t)
IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1687 NVIC->ICPR[(((uint32_t)(int32_t)
IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1700 return((uint32_t)(((
NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1713 if ((int32_t)(IRQn) < 0)
1715 SCB->SHP[(((uint32_t)(int32_t)
IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U -
__NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1736 if ((int32_t)(IRQn) < 0)
1738 return(((uint32_t)
SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U -
__NVIC_PRIO_BITS)));
1758 __STATIC_INLINE uint32_t
NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1760 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);
1761 uint32_t PreemptPriorityBits;
1762 uint32_t SubPriorityBits;
1765 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(
__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(
__NVIC_PRIO_BITS));
1768 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1769 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1785 __STATIC_INLINE
void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t*
const pPreemptPriority, uint32_t*
const pSubPriority)
1787 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);
1788 uint32_t PreemptPriorityBits;
1789 uint32_t SubPriorityBits;
1792 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(
__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(
__NVIC_PRIO_BITS));
1794 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1795 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1830 #if (__Vendor_SysTickConfig == 0U) 1850 SysTick->LOAD = (uint32_t)(ticks - 1UL);
1874 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5U 1888 ((
ITM->TER & 1UL ) != 0UL) )
1890 while (
ITM->PORT[0U].u32 == 0UL)
1894 ITM->PORT[0U].u8 = (uint8_t)ch;
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
CMSIS Cortex-M Core Function Access Header File.
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
#define SCB_AIRCR_VECTKEY_Pos
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
#define SysTick_CTRL_CLKSOURCE_Msk
Structure type to access the System Control Block (SCB).
Structure type to access the Data Watchpoint and Trace Register (DWT).
CMSIS Cortex-M Core Instruction Access Header File.
__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch)
ITM Send Character.
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
#define ITM_RXBUFFER_EMPTY
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
volatile int32_t ITM_RxBuffer
#define SysTick_CTRL_TICKINT_Msk
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Disable External Interrupt.
Structure type to access the System Timer (SysTick).
Structure type to access the Core Debug Register (CoreDebug).
CMSIS Cortex-M SIMD Header File.
__STATIC_INLINE void NVIC_SystemReset(void)
System Reset.
Union type to access the Application Program Status Register (APSR).
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Enable External Interrupt.
#define SCB_AIRCR_VECTKEY_Msk
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
__STATIC_INLINE uint32_t NVIC_IsIRQEnabled(IRQn_Type IRQn)
Get External Interrupt Enable State.
__STATIC_INLINE void __NOP(void)
No Operation.
#define SCB_AIRCR_PRIGROUP_Msk
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
System Tick Configuration.
Union type to access the Control Registers (CONTROL).
Structure type to access the Trace Port Interface Register (TPI).
#define SysTick_LOAD_RELOAD_Msk
Structure type to access the System Control and ID Register not in the SCB.
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
__STATIC_INLINE void __DSB(void)
Data Synchronization Barrier.
Union type to access the Interrupt Program Status Register (IPSR).
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Union type to access the Special-Purpose Program Status Registers (xPSR).
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
#define SysTick_CTRL_ENABLE_Msk
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
#define __NVIC_PRIO_BITS
Number of Bits used for Priority Levels.
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
#define ITM_TCR_ITMENA_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
#define SCB_AIRCR_PRIGROUP_Pos