50 #ifndef CC13XX_CC26XX_CM4_H_ 51 #define CC13XX_CC26XX_CM4_H_ 105 } cc13xx_cc26xx_cm4_irq_t;
107 typedef cc13xx_cc26xx_cm4_irq_t IRQn_Type;
109 #define SysTick_IRQn CC13XX_CC26XX_CM4_EXCEPTION_SYS_TICK 116 #define __MPU_PRESENT 1 117 #define __NVIC_PRIO_BITS 3 118 #define __Vendor_SysTickConfig 0
19 AON SpiSplave Rx, Tx and CS
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
46 Dynamic Programmable interrupt (default source: PRCM)
22 Sensor Controller software event 0, through AON domain
27 RF Core Command Acknowledge
39 Crypto Core Result available
44 AUX combined event, directly to MCU domain
29 Sensor Controller software event 1, through AON domain
25 RF Command and Packet Engine 0
18 RF Command and Packet Engine 1