Contiki-NG
sys-ctrl.h
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1 /*
2  * Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution.
13  *
14  * 3. Neither the name of the copyright holder nor the names of its
15  * contributors may be used to endorse or promote products derived
16  * from this software without specific prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
21  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
22  * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
23  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
27  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
29  * OF THE POSSIBILITY OF SUCH DAMAGE.
30  */
31 /**
32  * \addtogroup cc2538
33  * @{
34  *
35  * \defgroup cc2538-sys-ctrl cc2538 System Control (SysCtrl)
36  *
37  * Driver for the cc2538 System Control Module
38  * @{
39  *
40  * \file
41  * Header file for the cc2538 System Control driver
42  */
43 #ifndef SYS_CTRL_H_
44 #define SYS_CTRL_H_
45 
46 #include <stdint.h>
47 /*---------------------------------------------------------------------------*/
48 /** \name SysCtrl Constants, used by the SYS_DIV and IO_DIV bits of the
49  * SYS_CTRL_CLOCK_CTRL register
50  * @{
51  */
52 #define SYS_CTRL_32MHZ 32000000
53 #define SYS_CTRL_16MHZ 16000000
54 #define SYS_CTRL_8MHZ 8000000
55 #define SYS_CTRL_4MHZ 4000000
56 #define SYS_CTRL_2MHZ 2000000
57 #define SYS_CTRL_1MHZ 1000000
58 #define SYS_CTRL_500KHZ 500000
59 #define SYS_CTRL_250KHZ 250000
60 /** @} */
61 /*---------------------------------------------------------------------------*/
62 /** \name Definitions of Sys Ctrl registers
63  * @{
64  */
65 #define SYS_CTRL_CLOCK_CTRL 0x400D2000 /**< Clock control register */
66 #define SYS_CTRL_CLOCK_STA 0x400D2004 /**< Clock status register */
67 #define SYS_CTRL_RCGCGPT 0x400D2008 /**< GPT[3:0] clocks - active mode */
68 #define SYS_CTRL_SCGCGPT 0x400D200C /**< GPT[3:0] clocks - sleep mode */
69 #define SYS_CTRL_DCGCGPT 0x400D2010 /**< GPT[3:0] clocks - PM0 */
70 #define SYS_CTRL_SRGPT 0x400D2014 /**< GPT[3:0] reset control */
71 #define SYS_CTRL_RCGCSSI 0x400D2018 /**< SSI[1:0] clocks - active mode */
72 #define SYS_CTRL_SCGCSSI 0x400D201C /**< SSI[1:0] clocks - sleep mode */
73 #define SYS_CTRL_DCGCSSI 0x400D2020 /**< SSI[1:0] clocks - PM0 mode */
74 #define SYS_CTRL_SRSSI 0x400D2024 /**< SSI[1:0] reset control */
75 #define SYS_CTRL_RCGCUART 0x400D2028 /**< UART[1:0] clocks - active mode */
76 #define SYS_CTRL_SCGCUART 0x400D202C /**< UART[1:0] clocks - sleep mode */
77 #define SYS_CTRL_DCGCUART 0x400D2030 /**< UART[1:0] clocks - PM0 */
78 #define SYS_CTRL_SRUART 0x400D2034 /**< UART[1:0] reset control */
79 #define SYS_CTRL_RCGCI2C 0x400D2038 /**< I2C clocks - active mode */
80 #define SYS_CTRL_SCGCI2C 0x400D203C /**< I2C clocks - sleep mode */
81 #define SYS_CTRL_DCGCI2C 0x400D2040 /**< I2C clocks - PM0 */
82 #define SYS_CTRL_SRI2C 0x400D2044 /**< I2C clocks - reset control */
83 #define SYS_CTRL_RCGCSEC 0x400D2048 /**< Sec Mod clocks - active mode */
84 #define SYS_CTRL_SCGCSEC 0x400D204C /**< Sec Mod clocks - sleep mode */
85 #define SYS_CTRL_DCGCSEC 0x400D2050 /**< Sec Mod clocks - PM0 */
86 #define SYS_CTRL_SRSEC 0x400D2054 /**< Sec Mod reset control */
87 #define SYS_CTRL_PMCTL 0x400D2058 /**< Power Mode Control */
88 #define SYS_CTRL_SRCRC 0x400D205C /**< CRC on state retention */
89 #define SYS_CTRL_PWRDBG 0x400D2074 /**< Power debug register */
90 #define SYS_CTRL_CLD 0x400D2080 /**< clock loss detection feature */
91 #define SYS_CTRL_IWE 0x400D2094 /**< interrupt wake-up. */
92 #define SYS_CTRL_I_MAP 0x400D2098 /**< Interrupt map select */
93 #define SYS_CTRL_RCGCRFC 0x400D20A8 /**< RF Core clocks - active mode */
94 #define SYS_CTRL_SCGCRFC 0x400D20AC /**< RF Core clocks - Sleep mode */
95 #define SYS_CTRL_DCGCRFC 0x400D20B0 /**< RF Core clocks - PM0 */
96 #define SYS_CTRL_EMUOVR 0x400D20B4 /**< Emulator override */
97 /** @} */
98 /*---------------------------------------------------------------------------*/
99 /** \name SYS_CTRL_CLOCK_CTRL register bit masks
100  * @{
101  */
102 #define SYS_CTRL_CLOCK_CTRL_OSC32K_CALDIS 0x02000000
103 #define SYS_CTRL_CLOCK_CTRL_OSC32K 0x01000000
104 #define SYS_CTRL_CLOCK_CTRL_AMP_DET 0x00200000
105 #define SYS_CTRL_CLOCK_CTRL_OSC_PD 0x00020000
106 #define SYS_CTRL_CLOCK_CTRL_OSC 0x00010000
107 #define SYS_CTRL_CLOCK_CTRL_IO_DIV 0x00000700
108 #define SYS_CTRL_CLOCK_CTRL_SYS_DIV 0x00000007
109 /** @} */
110 /*---------------------------------------------------------------------------*/
111 /** \name SYS_CTRL_CLOCK_STA register bit masks
112  * @{
113  */
114 #define SYS_CTRL_CLOCK_STA_SYNC_32K 0x04000000
115 #define SYS_CTRL_CLOCK_STA_OSC32K_CALDIS 0x02000000
116 #define SYS_CTRL_CLOCK_STA_OSC32K 0x01000000
117 #define SYS_CTRL_CLOCK_STA_RST 0x00C00000
118 #define SYS_CTRL_CLOCK_STA_RST_S 22
119 #define SYS_CTRL_CLOCK_STA_RST_POR 0
120 #define SYS_CTRL_CLOCK_STA_RST_EXT 1
121 #define SYS_CTRL_CLOCK_STA_RST_WDT 2
122 #define SYS_CTRL_CLOCK_STA_RST_CLD_SW 3
123 #define SYS_CTRL_CLOCK_STA_SOURCE_CHANGE 0x00100000
124 #define SYS_CTRL_CLOCK_STA_XOSC_STB 0x00080000
125 #define SYS_CTRL_CLOCK_STA_HSOSC_STB 0x00040000
126 #define SYS_CTRL_CLOCK_STA_OSC_PD 0x00020000
127 #define SYS_CTRL_CLOCK_STA_OSC 0x00010000
128 #define SYS_CTRL_CLOCK_STA_IO_DIV 0x00000700
129 #define SYS_CTRL_CLOCK_STA_RTCLK_FREQ 0x00000018
130 #define SYS_CTRL_CLOCK_STA_SYS_DIV 0x00000007
131 /** @} */
132 /*---------------------------------------------------------------------------*/
133 /** \name SYS_CTRL_RCGCGPT register bit masks
134  * @{
135  */
136 #define SYS_CTRL_RCGCGPT_GPT3 0x00000008 /**< GPT3 clock enable, CPU running */
137 #define SYS_CTRL_RCGCGPT_GPT2 0x00000004 /**< GPT2 clock enable, CPU running */
138 #define SYS_CTRL_RCGCGPT_GPT1 0x00000002 /**< GPT1 clock enable, CPU running */
139 #define SYS_CTRL_RCGCGPT_GPT0 0x00000001 /**< GPT0 clock enable, CPU running */
140 /** @} */
141 /*---------------------------------------------------------------------------*/
142 /** \name SYS_CTRL_SCGCGPT register bit masks
143  * @{
144  */
145 #define SYS_CTRL_SCGCGPT_GPT3 0x00000008 /**< GPT3 clock enable, CPU IDLE */
146 #define SYS_CTRL_SCGCGPT_GPT2 0x00000004 /**< GPT2 clock enable, CPU IDLE */
147 #define SYS_CTRL_SCGCGPT_GPT1 0x00000002 /**< GPT1 clock enable, CPU IDLE */
148 #define SYS_CTRL_SCGCGPT_GPT0 0x00000001 /**< GPT0 clock enable, CPU IDLE */
149 /** @} */
150 /*---------------------------------------------------------------------------*/
151 /** \name SYS_CTRL_DCGCGPT register bit masks
152  * @{
153  */
154 #define SYS_CTRL_DCGCGPT_GPT3 0x00000008 /**< GPT3 clock enable, PM0 */
155 #define SYS_CTRL_DCGCGPT_GPT2 0x00000004 /**< GPT2 clock enable, PM0 */
156 #define SYS_CTRL_DCGCGPT_GPT1 0x00000002 /**< GPT1 clock enable, PM0 */
157 #define SYS_CTRL_DCGCGPT_GPT0 0x00000001 /**< GPT0 clock enable, PM0 */
158 /** @} */
159 /*---------------------------------------------------------------------------*/
160 /** \name SYS_CTRL_SRGPT register bits
161  * @{
162  */
163 #define SYS_CTRL_SRGPT_GPT3 0x00000008 /**< GPT3 is reset */
164 #define SYS_CTRL_SRGPT_GPT2 0x00000004 /**< GPT2 is reset */
165 #define SYS_CTRL_SRGPT_GPT1 0x00000002 /**< GPT1 is reset */
166 #define SYS_CTRL_SRGPT_GPT0 0x00000001 /**< GPT0 is reset */
167 /** @} */
168 /*---------------------------------------------------------------------------*/
169 /** \name SYS_CTRL_RCGCSEC register bit masks
170  * @{
171  */
172 #define SYS_CTRL_RCGCSEC_AES 0x00000002 /**< AES clock enable, CPU running */
173 #define SYS_CTRL_RCGCSEC_PKA 0x00000001 /**< PKA clock enable, CPU running */
174 /** @} */
175 /*---------------------------------------------------------------------------*/
176 /** \name SYS_CTRL_SCGCSEC register bit masks
177  * @{
178  */
179 #define SYS_CTRL_SCGCSEC_AES 0x00000002 /**< AES clock enable, CPU IDLE */
180 #define SYS_CTRL_SCGCSEC_PKA 0x00000001 /**< PKA clock enable, CPU IDLE */
181 /** @} */
182 /*---------------------------------------------------------------------------*/
183 /** \name SYS_CTRL_DCGCSEC register bit masks
184  * @{
185  */
186 #define SYS_CTRL_DCGCSEC_AES 0x00000002 /**< AES clock enable, PM0 */
187 #define SYS_CTRL_DCGCSEC_PKA 0x00000001 /**< PKA clock enable, PM0 */
188 /** @} */
189 /*---------------------------------------------------------------------------*/
190 /** \name SYS_CTRL_SRSEC register bits
191  * @{
192  */
193 #define SYS_CTRL_SRSEC_AES 0x00000002 /**< AES is reset */
194 #define SYS_CTRL_SRSEC_PKA 0x00000001 /**< PKA is reset */
195 /** @} */
196 /*---------------------------------------------------------------------------*/
197 /** \name SYS_CTRL_PWRDBG register bits
198  * @{
199  */
200 #define SYS_CTRL_PWRDBG_FORCE_WARM_RESET 0x00000008
201 /** @} */
202 /*---------------------------------------------------------------------------*/
203 /** \name Possible values for the SYS_CTRL_CLOCK_CTRL_SYS_DIV bits
204  * @{
205  */
206 #define SYS_CTRL_CLOCK_CTRL_SYS_DIV_32MHZ 0x00000000
207 #define SYS_CTRL_CLOCK_CTRL_SYS_DIV_16MHZ 0x00000001
208 #define SYS_CTRL_CLOCK_CTRL_SYS_DIV_8MHZ 0x00000002
209 #define SYS_CTRL_CLOCK_CTRL_SYS_DIV_4MHZ 0x00000003
210 #define SYS_CTRL_CLOCK_CTRL_SYS_DIV_2MHZ 0x00000004
211 #define SYS_CTRL_CLOCK_CTRL_SYS_DIV_1MHZ 0x00000005
212 #define SYS_CTRL_CLOCK_CTRL_SYS_DIV_500KHZ 0x00000006
213 #define SYS_CTRL_CLOCK_CTRL_SYS_DIV_250KHZ 0x00000007
214 /** @} */
215 /*---------------------------------------------------------------------------*/
216 /** \name Possible values for the SYS_CTRL_CLOCK_CTRL_IO_DIV bits
217  * @{
218  */
219 #define SYS_CTRL_CLOCK_CTRL_IO_DIV_32MHZ 0x00000000
220 #define SYS_CTRL_CLOCK_CTRL_IO_DIV_16MHZ 0x00000100
221 #define SYS_CTRL_CLOCK_CTRL_IO_DIV_8MHZ 0x00000200
222 #define SYS_CTRL_CLOCK_CTRL_IO_DIV_4MHZ 0x00000300
223 #define SYS_CTRL_CLOCK_CTRL_IO_DIV_2MHZ 0x00000400
224 #define SYS_CTRL_CLOCK_CTRL_IO_DIV_1MHZ 0x00000500
225 #define SYS_CTRL_CLOCK_CTRL_IO_DIV_500KHZ 0x00000600
226 #define SYS_CTRL_CLOCK_CTRL_IO_DIV_250KHZ 0x00000700
227 /** @} */
228 /*---------------------------------------------------------------------------*/
229 /** \name SYS_CTRL_RCGCUART Register Bit-Masks
230  * @{
231  */
232 #define SYS_CTRL_RCGCUART_UART1 0x00000002 /**< UART1 Clock, CPU running */
233 #define SYS_CTRL_RCGCUART_UART0 0x00000001 /**< UART0 Clock, CPU running */
234 /** @} */
235 /*---------------------------------------------------------------------------*/
236 /** \name SYS_CTRL_SCGCUART Register Bit-Masks
237  * @{
238  */
239 #define SYS_CTRL_SCGCUART_UART1 0x00000002 /**< UART1 Clock, CPU IDLE */
240 #define SYS_CTRL_SCGCUART_UART0 0x00000001 /**< UART0 Clock, CPU IDLE */
241 /** @} */
242 /*---------------------------------------------------------------------------*/
243 /** \name SYS_CTRL_RCGCUART Register Bit-Masks
244  * @{
245  */
246 #define SYS_CTRL_DCGCUART_UART1 0x00000002 /**< UART1 Clock, PM0 */
247 #define SYS_CTRL_DCGCUART_UART0 0x00000001 /**< UART0 Clock, PM0 */
248 /** @} */
249 /*---------------------------------------------------------------------------*/
250 /** \name SYS_CTRL_SRUART register bits
251  * @{
252  */
253 #define SYS_CTRL_SRUART_UART1 0x00000002 /**< UART1 module is reset */
254 #define SYS_CTRL_SRUART_UART0 0x00000001 /**< UART0 module is reset */
255 /** @} */
256 /*---------------------------------------------------------------------------*/
257 /** \name SYS_CTRL_PMCTL register values
258  * @{
259  */
260 #define SYS_CTRL_PMCTL_PM3 0x00000003 /**< PM3 */
261 #define SYS_CTRL_PMCTL_PM2 0x00000002 /**< PM2 */
262 #define SYS_CTRL_PMCTL_PM1 0x00000001 /**< PM1 */
263 #define SYS_CTRL_PMCTL_PM0 0x00000000 /**< PM0 */
264 /** @} */
265 /*---------------------------------------------------------------------------*/
266 /** \name SysCtrl 32-kHz oscillator selection
267  *
268  * Prefer the crystal oscillator for time accuracy, and the RC oscillator for
269  * cost and power consumption
270  * @{
271  */
272 /* Defaults to RC oscillator unless the configuration tells us otherwise */
273 #ifdef SYS_CTRL_CONF_OSC32K_USE_XTAL
274 #define SYS_CTRL_OSC32K_USE_XTAL SYS_CTRL_CONF_OSC32K_USE_XTAL
275 #else
276 #define SYS_CTRL_OSC32K_USE_XTAL 0
277 #endif
278 /** @} */
279 /*---------------------------------------------------------------------------*/
280 /** \name System clock divisor selection
281  * @{
282  */
283 #ifdef SYS_CTRL_CONF_SYS_DIV
284 #if SYS_CTRL_CONF_SYS_DIV & ~SYS_CTRL_CLOCK_CTRL_SYS_DIV
285 #error Invalid system clock divisor
286 #endif
287 #define SYS_CTRL_SYS_DIV SYS_CTRL_CONF_SYS_DIV
288 #else
289 #define SYS_CTRL_SYS_DIV SYS_CTRL_CLOCK_CTRL_SYS_DIV_16MHZ
290 #endif
291 
292 #ifdef SYS_CTRL_CONF_IO_DIV
293 #if SYS_CTRL_CONF_IO_DIV & ~SYS_CTRL_CLOCK_CTRL_IO_DIV
294 #error Invalid I/O clock divisor
295 #endif
296 #define SYS_CTRL_IO_DIV SYS_CTRL_CONF_IO_DIV
297 #else
298 #define SYS_CTRL_IO_DIV SYS_CTRL_CLOCK_CTRL_IO_DIV_16MHZ
299 #endif
300 
301 /* Returns actual system clock in Hz */
302 #define SYS_CTRL_SYS_CLOCK (SYS_CTRL_32MHZ >> SYS_CTRL_SYS_DIV)
303 /* Returns actual I/O clock in Hz */
304 #define SYS_CTRL_IO_CLOCK (SYS_CTRL_32MHZ >> (SYS_CTRL_IO_DIV >> 8))
305 /** @} */
306 /*---------------------------------------------------------------------------*/
307 /** \name SysCtrl functions
308  * @{
309  */
310 
311 /** \brief Gets the cause of the last reset
312  * \return A \c SYS_CTRL_CLOCK_STA_RST_x reset cause
313  */
314 int sys_ctrl_get_reset_cause(void);
315 
316 /** \brief Gets a string describing the cause of the last reset
317  * \return Last reset cause as a string
318  */
319 const char *sys_ctrl_get_reset_cause_str(void);
320 
321 /** \brief Initialises the System Control Driver. The main purpose of this
322  * function is to power up and select clocks and oscillators
323  * \note This function depends on ioc_init() having been called beforehand. */
324 void sys_ctrl_init();
325 
326 /** \brief Generates a warm reset through the SYS_CTRL_PWRDBG register */
327 void sys_ctrl_reset();
328 
329 /** \brief Returns the actual system clock in Hz */
330 uint32_t sys_ctrl_get_sys_clock();
331 
332 /** \brief Returns the actual io clock in Hz */
333 uint32_t sys_ctrl_get_io_clock();
334 
335 /** @} */
336 
337 #endif /* SYS_CTRL_H_ */
338 
339 /**
340  * @}
341  * @}
342  */
const char * sys_ctrl_get_reset_cause_str(void)
Gets a string describing the cause of the last reset.
Definition: sys-ctrl.c:61
uint32_t sys_ctrl_get_io_clock(void)
Returns the actual io clock in Hz.
Definition: sys-ctrl.c:127
int sys_ctrl_get_reset_cause(void)
Gets the cause of the last reset.
Definition: sys-ctrl.c:54
uint32_t sys_ctrl_get_sys_clock(void)
Returns the actual system clock in Hz.
Definition: sys-ctrl.c:120
void sys_ctrl_init()
Initialises the System Control Driver.
Definition: sys-ctrl.c:74
void sys_ctrl_reset()
Generates a warm reset through the SYS_CTRL_PWRDBG register.
Definition: sys-ctrl.c:114