Contiki-NG
spi-legacy.c
1 /*
2  * Copyright (c) 2006, Swedish Institute of Computer Science
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution.
13  * 3. Neither the name of the Institute nor the names of its contributors
14  * may be used to endorse or promote products derived from this software
15  * without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  */
29 
30 #include "contiki.h"
31 
32 /*
33  * This is SPI initialization code for the MSP430X architecture.
34  *
35  */
36 unsigned char spi_busy = 0;
37 
38 /*
39  * Initialize SPI bus.
40  */
41 void
42 spi_init(void)
43 {
44  // Initialize ports for communication with SPI units.
45 
46  UCB0CTL1 |= UCSWRST; //reset usci
47  UCB0CTL1 |= UCSSEL_2; //smclk while usci is reset
48  UCB0CTL0 = ( UCMSB | UCMST | UCSYNC | UCCKPL); // MSB-first 8-bit, Master, Synchronous, 3 pin SPI master, no ste, watch-out for clock-phase UCCKPH
49 
50  UCB0BR1 = 0x00;
51  UCB0BR0 = 0x02;
52 
53 // UCB0MCTL = 0; // Dont need modulation control.
54 
55  P3SEL |= BV(SCK) | BV(MOSI) | BV(MISO); // Select Peripheral functionality
56  P3DIR |= BV(SCK) | BV(MISO); // Configure as outputs(SIMO,CLK).
57 
58  //ME1 |= USPIE0; // Module enable ME1 --> U0ME? xxx/bg
59 
60  // Clear pending interrupts before enable!!!
61  IFG2 &= ~UCB0RXIFG;
62  IFG2 &= ~UCB0TXIFG;
63  /* UCB0IE &= ~UCRXIFG; */
64  /* UCB0IE &= ~UCTXIFG; */
65  UCB0CTL1 &= ~UCSWRST; // Remove RESET before enabling interrupts
66 
67  //Enable UCB0 Interrupts
68  //IE2 |= UCB0TXIE; // Enable USCI_B0 TX Interrupts
69  //IE2 |= UCB0RXIE; // Enable USCI_B0 RX Interrupts
70 }