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Structure type to access the Core Debug Register (CoreDebug). More...
#include <arch/cpu/arm/cortex-m/CMSIS/core_cm3.h>
Data Fields | |
__IOM uint32_t | DHCSR |
__OM uint32_t | DCRSR |
__IOM uint32_t | DCRDR |
__IOM uint32_t | DEMCR |
Structure type to access the Core Debug Register (CoreDebug).
Definition at line 1235 of file core_cm3.h.
__IOM uint32_t CoreDebug_Type::DCRDR |
Offset: 0x008 (R/W) Debug Core Register Data Register
Definition at line 1239 of file core_cm3.h.
__OM uint32_t CoreDebug_Type::DCRSR |
Offset: 0x004 ( /W) Debug Core Register Selector Register
Definition at line 1238 of file core_cm3.h.
__IOM uint32_t CoreDebug_Type::DEMCR |
Offset: 0x00C (R/W) Debug Exception and Monitor Control Register
Definition at line 1240 of file core_cm3.h.
__IOM uint32_t CoreDebug_Type::DHCSR |
Offset: 0x000 (R/W) Debug Halting Control and Status Register
Definition at line 1237 of file core_cm3.h.