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startup_cc13xx_cc26xx_iar.c
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1 /*
2  * Copyright (c) 2018, Texas Instruments Incorporated - http://www.ti.com/
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution.
13  * 3. Neither the name of the copyright holder nor the names of its
14  * contributors may be used to endorse or promote products derived
15  * from this software without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
20  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
21  * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
23  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
24  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
26  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
28  * OF THE POSSIBILITY OF SUCH DAMAGE.
29  */
30 /**
31  * \addtogroup cc13xx-cc26xx-cpu
32  * @{
33  *
34  * \file
35  * Startup file for IAR for CC13xx/CC26xx.
36  */
37 /*---------------------------------------------------------------------------*/
38 /* Check if compiler is IAR. */
39 #if !(defined(__IAR_SYSTEMS_ICC__))
40 #error "startup_cc13xx_cc26xx_iar.c: Unsupported compiler!"
41 #endif
42 /*---------------------------------------------------------------------------*/
43 /* We need intrinsic functions for IAR (if used in source code). */
44 #include <intrinsics.h>
45 
46 #include <ti/devices/DeviceFamily.h>
47 #include DeviceFamily_constructPath(inc/hw_types.h)
48 #include DeviceFamily_constructPath(driverlib/setup.h)
49 #include DeviceFamily_constructPath(driverlib/interrupt.h)
50 /*---------------------------------------------------------------------------*/
51 /* Forward declaration of the reset ISR and the default fault handlers. */
52 static void nmiISR(void);
53 static void faultISR(void);
54 static void intDefaultHandler(void);
55 extern int main(void);
56 
57 extern void MPUFaultIntHandler(void);
58 extern void BusFaultIntHandler(void);
59 extern void UsageFaultIntHandler(void);
60 extern void SVCallIntHandler(void);
61 extern void DebugMonIntHandler(void);
62 extern void PendSVIntHandler(void);
63 extern void SysTickIntHandler(void);
64 extern void GPIOIntHandler(void);
65 extern void I2CIntHandler(void);
66 extern void RFCCPE1IntHandler(void);
67 extern void AONRTCIntHandler(void);
68 extern void UART0IntHandler(void);
69 extern void AUXSWEvent0IntHandler(void);
70 extern void SSI0IntHandler(void);
71 extern void SSI1IntHandler(void);
72 extern void RFCCPE0IntHandler(void);
73 extern void RFCHardwareIntHandler(void);
74 extern void RFCCmdAckIntHandler(void);
75 extern void I2SIntHandler(void);
76 extern void AUXSWEvent1IntHandler(void);
77 extern void WatchdogIntHandler(void);
78 extern void Timer0AIntHandler(void);
79 extern void Timer0BIntHandler(void);
80 extern void Timer1AIntHandler(void);
81 extern void Timer1BIntHandler(void);
82 extern void Timer2AIntHandler(void);
83 extern void Timer2BIntHandler(void);
84 extern void Timer3AIntHandler(void);
85 extern void Timer3BIntHandler(void);
86 extern void CryptoIntHandler(void);
87 extern void uDMAIntHandler(void);
88 extern void uDMAErrIntHandler(void);
89 extern void FlashIntHandler(void);
90 extern void SWEvent0IntHandler(void);
91 extern void AUXCombEventIntHandler(void);
92 extern void AONProgIntHandler(void);
93 extern void DynProgIntHandler(void);
94 extern void AUXCompAIntHandler(void);
95 extern void AUXADCIntHandler(void);
96 extern void TRNGIntHandler(void);
97 
98 /* Default interrupt handlers */
99 #pragma weak MPUFaultIntHandler = intDefaultHandler
100 #pragma weak BusFaultIntHandler = intDefaultHandler
101 #pragma weak UsageFaultIntHandler = intDefaultHandler
102 #pragma weak SVCallIntHandler = intDefaultHandler
103 #pragma weak DebugMonIntHandler = intDefaultHandler
104 #pragma weak PendSVIntHandler = intDefaultHandler
105 #pragma weak SysTickIntHandler = intDefaultHandler
106 #pragma weak GPIOIntHandler = intDefaultHandler
107 #pragma weak I2CIntHandler = intDefaultHandler
108 #pragma weak RFCCPE1IntHandler = intDefaultHandler
109 #pragma weak AONRTCIntHandler = intDefaultHandler
110 #pragma weak UART0IntHandler = intDefaultHandler
111 #pragma weak AUXSWEvent0IntHandler = intDefaultHandler
112 #pragma weak SSI0IntHandler = intDefaultHandler
113 #pragma weak SSI1IntHandler = intDefaultHandler
114 #pragma weak RFCCPE0IntHandler = intDefaultHandler
115 #pragma weak RFCHardwareIntHandler = intDefaultHandler
116 #pragma weak RFCCmdAckIntHandler = intDefaultHandler
117 #pragma weak I2SIntHandler = intDefaultHandler
118 #pragma weak AUXSWEvent1IntHandler = intDefaultHandler
119 #pragma weak WatchdogIntHandler = intDefaultHandler
120 #pragma weak Timer0AIntHandler = intDefaultHandler
121 #pragma weak Timer0BIntHandler = intDefaultHandler
122 #pragma weak Timer1AIntHandler = intDefaultHandler
123 #pragma weak Timer1BIntHandler = intDefaultHandler
124 #pragma weak Timer2AIntHandler = intDefaultHandler
125 #pragma weak Timer2BIntHandler = intDefaultHandler
126 #pragma weak Timer3AIntHandler = intDefaultHandler
127 #pragma weak Timer3BIntHandler = intDefaultHandler
128 #pragma weak CryptoIntHandler = intDefaultHandler
129 #pragma weak uDMAIntHandler = intDefaultHandler
130 #pragma weak uDMAErrIntHandler = intDefaultHandler
131 #pragma weak FlashIntHandler = intDefaultHandler
132 #pragma weak SWEvent0IntHandler = intDefaultHandler
133 #pragma weak AUXCombEventIntHandler = intDefaultHandler
134 #pragma weak AONProgIntHandler = intDefaultHandler
135 #pragma weak DynProgIntHandler = intDefaultHandler
136 #pragma weak AUXCompAIntHandler = intDefaultHandler
137 #pragma weak AUXADCIntHandler = intDefaultHandler
138 #pragma weak TRNGIntHandler = intDefaultHandler
139 /*---------------------------------------------------------------------------*/
140 /* The entry point for the application startup code. */
141 extern void __iar_program_start(void);
142 
143 /* Get stack start (highest address) symbol from linker file. */
144 extern const void *STACK_TOP;
145 /*---------------------------------------------------------------------------*/
146 /*
147  * It is required to place something in the CSTACK segment to get the stack
148  * check feature in IAR to work as expected
149  */
150 __root static void *dummy_stack @ ".stack";
151 
152 /*
153  * The vector table. Note that the proper constructs must be placed on this to
154  * ensure that it ends up at physical address 0x0000.0000 or at the start of
155  * the program if located at a start address other than 0.
156  */
157 __root void(*const __vector_table[])(void) @ ".intvec" =
158 {
159  (void (*)(void)) & STACK_TOP, /* 0 The initial stack pointer */
160  __iar_program_start, /* 1 The reset handler */
161  nmiISR, /* 2 The NMI handler */
162  faultISR, /* 3 The hard fault handler */
163  MPUFaultIntHandler, /* 4 The MPU fault handler */
164  BusFaultIntHandler, /* 5 The bus fault handler */
165  UsageFaultIntHandler, /* 6 The usage fault handler */
166  0, /* 7 Reserved */
167  0, /* 8 Reserved */
168  0, /* 9 Reserved */
169  0, /* 10 Reserved */
170  SVCallIntHandler, /* 11 SVCall handler */
171  DebugMonIntHandler, /* 12 Debug monitor handler */
172  0, /* 13 Reserved */
173  PendSVIntHandler, /* 14 The PendSV handler */
174  SysTickIntHandler, /* 15 The SysTick handler */
175  /* --- External interrupts --- */
176  GPIOIntHandler, /* 16 AON edge detect */
177  I2CIntHandler, /* 17 I2C */
178  RFCCPE1IntHandler, /* 18 RF Core Command & Packet Engine 1 */
179  intDefaultHandler, /* 19 Reserved */
180  AONRTCIntHandler, /* 20 AON RTC */
181  UART0IntHandler, /* 21 UART0 Rx and Tx */
182  AUXSWEvent0IntHandler, /* 22 AUX software event 0 */
183  SSI0IntHandler, /* 23 SSI0 Rx and Tx */
184  SSI1IntHandler, /* 24 SSI1 Rx and Tx */
185  RFCCPE0IntHandler, /* 25 RF Core Command & Packet Engine 0 */
186  RFCHardwareIntHandler, /* 26 RF Core Hardware */
187  RFCCmdAckIntHandler, /* 27 RF Core Command Acknowledge */
188  I2SIntHandler, /* 28 I2S */
189  AUXSWEvent1IntHandler, /* 29 AUX software event 1 */
190  WatchdogIntHandler, /* 30 Watchdog timer */
191  Timer0AIntHandler, /* 31 Timer 0 subtimer A */
192  Timer0BIntHandler, /* 32 Timer 0 subtimer B */
193  Timer1AIntHandler, /* 33 Timer 1 subtimer A */
194  Timer1BIntHandler, /* 34 Timer 1 subtimer B */
195  Timer2AIntHandler, /* 35 Timer 2 subtimer A */
196  Timer2BIntHandler, /* 36 Timer 2 subtimer B */
197  Timer3AIntHandler, /* 37 Timer 3 subtimer A */
198  Timer3BIntHandler, /* 38 Timer 3 subtimer B */
199  CryptoIntHandler, /* 39 Crypto Core Result available */
200  uDMAIntHandler, /* 40 uDMA Software */
201  uDMAErrIntHandler, /* 41 uDMA Error */
202  FlashIntHandler, /* 42 Flash controller */
203  SWEvent0IntHandler, /* 43 Software Event 0 */
204  AUXCombEventIntHandler, /* 44 AUX combined event */
205  AONProgIntHandler, /* 45 AON programmable 0 */
206  DynProgIntHandler, /* 46 Dynamic Programmable interrupt */
207  /* source (Default: PRCM) */
208  AUXCompAIntHandler, /* 47 AUX Comparator A */
209  AUXADCIntHandler, /* 48 AUX ADC new sample or ADC DMA */
210  /* done, ADC underflow, ADC overflow */
211  TRNGIntHandler /* 49 TRNG event */
212 }
213 /*---------------------------------------------------------------------------*/
214 /*
215  * \brief Setup trim device.
216  * \return Return value determines whether to omit seg_init or not.
217  * 0 => omit seg_init
218  * 1 => run seg_init
219  *
220  * This function is called by __iar_program_start() early in the boot sequence.
221  * Copy the first 16 vectors from the read-only/reset table to the runtime
222  * RAM table. Fill the remaining vectors with a stub. This vector table will
223  * be updated at runtime.
224  */
225 int
226 __low_level_init(void)
227 {
228  IntMasterDisable();
229 
230  /* Final trim of device */
231  SetupTrimDevice();
232 
233  /* Run seg_init */
234  return 1;
235 }
236 /*---------------------------------------------------------------------------*/
237 /*
238  * \brief Non-Maskable Interrupt (NMI) ISR.
239  *
240  * This is the code that gets called when the processor receives a NMI. This
241  * simply enters an infinite loop, preserving the system state for examination
242  * by a debugger.
243  */
244 static void
245 nmiISR(void)
246 {
247  /* Enter an infinite loop. */
248  for(;;) { /* hang */ }
249 }
250 /*---------------------------------------------------------------------------*/
251 /*
252  * \brief Debug stack pointer.
253  * \param sp Stack pointer.
254  *
255  * Provide a view into the CPU state from the provided stack pointer.
256  */
257 void
258 debugStackPointer(uint32_t *sp)
259 {
260  volatile uint32_t r0; /**< R0 register */
261  volatile uint32_t r1; /**< R1 register */
262  volatile uint32_t r2; /**< R2 register */
263  volatile uint32_t r3; /**< R3 register */
264  volatile uint32_t r12; /**< R12 register */
265  volatile uint32_t lr; /**< LR register */
266  volatile uint32_t pc; /**< PC register */
267  volatile uint32_t psr; /**< PSR register */
268 
269  /* Cast to void to disable warnings of unused variables */
270  (void)(r0 = sp[0]);
271  (void)(r1 = sp[1]);
272  (void)(r2 = sp[2]);
273  (void)(r3 = sp[3]);
274  (void)(r12 = sp[4]);
275  (void)(lr = sp[5]);
276  (void)(pc = sp[6]);
277  (void)(psr = sp[7]);
278 
279  /* Enter an infinite loop. */
280  for(;;) { /* hang */ }
281 }
282 /*---------------------------------------------------------------------------*/
283 /*
284  * \brief CPU Fault ISR.
285  *
286  * This is the code that gets called when the processor receives a fault
287  * interrupt. Setup a call to debugStackPointer with the current stack pointer.
288  * The stack pointer in this case would be the CPU state which caused the CPU
289  * fault.
290  */
291 static void
292 faultISR(void)
293 {
294  __asm__ __volatile__
295  (
296  "tst lr, #4 \n"
297  "ite eq \n"
298  "mrseq r0, msp \n"
299  "mrsne r0, psp \n"
300  "b debugStackPointer \n"
301  );
302 }
303 /*---------------------------------------------------------------------------*/
304 /*
305  * \brief Interrupt Default Handler.
306  *
307  * This is the code that gets called when the processor receives an unexpected
308  * interrupt. This simply enters an infinite loop, preserving the system state
309  * for examination by a debugger.
310  */
311 static void
312 intDefaultHandler(void)
313 {
314  /* Enter an infinite loop. */
315  for(;;) { /* hang */ }
316 }
317 /*---------------------------------------------------------------------------*/
318 /** @} */
void debugStackPointer(uint32_t *sp)