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rfcore-xreg.h
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1 /*
2  * Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution.
13  *
14  * 3. Neither the name of the copyright holder nor the names of its
15  * contributors may be used to endorse or promote products derived
16  * from this software without specific prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
21  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
22  * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
23  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
27  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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29  * OF THE POSSIBILITY OF SUCH DAMAGE.
30  */
31 /**
32  * \addtogroup cc2538-rfcore
33  * @{
34  *
35  * \file
36  * Header with declarations of the RF Core XREGs.
37  */
38 #ifndef RFCORE_XREG_H_
39 #define RFCORE_XREG_H_
40 /*---------------------------------------------------------------------------*/
41 /** \name RFCORE_FFSM register offsets
42  * @{
43  */
44 #define RFCORE_XREG_FRMFILT0 0x40088600 /**< Frame filtering control */
45 #define RFCORE_XREG_FRMFILT1 0x40088604 /**< Frame filtering control */
46 #define RFCORE_XREG_SRCMATCH 0x40088608 /**< Source address matching */
47 #define RFCORE_XREG_SRCSHORTEN0 0x4008860C /**< Short address matching */
48 #define RFCORE_XREG_SRCSHORTEN1 0x40088610 /**< Short address matching */
49 #define RFCORE_XREG_SRCSHORTEN2 0x40088614 /**< Short address matching */
50 #define RFCORE_XREG_SRCEXTEN0 0x40088618 /**< Extended address matching */
51 #define RFCORE_XREG_SRCEXTEN1 0x4008861C /**< Extended address matching */
52 #define RFCORE_XREG_SRCEXTEN2 0x40088620 /**< Extended address matching */
53 #define RFCORE_XREG_FRMCTRL0 0x40088624 /**< Frame handling */
54 #define RFCORE_XREG_FRMCTRL1 0x40088628 /**< Frame handling */
55 #define RFCORE_XREG_RXENABLE 0x4008862C /**< RX enabling */
56 #define RFCORE_XREG_RXMASKSET 0x40088630 /**< RX enabling */
57 #define RFCORE_XREG_RXMASKCLR 0x40088634 /**< RX disabling */
58 #define RFCORE_XREG_FREQTUNE 0x40088638 /**< Crystal oscillator freq tuning */
59 #define RFCORE_XREG_FREQCTRL 0x4008863C /**< Controls the RF frequency */
60 #define RFCORE_XREG_TXPOWER 0x40088640 /**< Controls the output power */
61 #define RFCORE_XREG_TXCTRL 0x40088644 /**< Controls the TX settings */
62 #define RFCORE_XREG_FSMSTAT0 0x40088648 /**< Radio status register */
63 #define RFCORE_XREG_FSMSTAT1 0x4008864C /**< Radio status register */
64 #define RFCORE_XREG_FIFOPCTRL 0x40088650 /**< FIFOP threshold */
65 #define RFCORE_XREG_FSMCTRL 0x40088654 /**< FSM options */
66 #define RFCORE_XREG_CCACTRL0 0x40088658 /**< CCA threshold */
67 #define RFCORE_XREG_CCACTRL1 0x4008865C /**< Other CCA Options */
68 #define RFCORE_XREG_RSSI 0x40088660 /**< RSSI status register */
69 #define RFCORE_XREG_RSSISTAT 0x40088664 /**< RSSI valid status register */
70 #define RFCORE_XREG_RXFIRST 0x40088668 /**< First byte in RX FIFO */
71 #define RFCORE_XREG_RXFIFOCNT 0x4008866C /**< Number of bytes in RX FIFO */
72 #define RFCORE_XREG_TXFIFOCNT 0x40088670 /**< Number of bytes in TX FIFO */
73 #define RFCORE_XREG_RXFIRST_PTR 0x40088674 /**< RX FIFO pointer */
74 #define RFCORE_XREG_RXLAST_PTR 0x40088678 /**< RX FIFO pointer */
75 #define RFCORE_XREG_RXP1_PTR 0x4008867C /**< RX FIFO pointer */
76 #define RFCORE_XREG_RXP2_PTR 0x40088680 /**< RX FIFO pointer */
77 #define RFCORE_XREG_TXFIRST_PTR 0x40088684 /**< TX FIFO pointer */
78 #define RFCORE_XREG_TXLAST_PTR 0x40088688 /**< TX FIFO pointer */
79 #define RFCORE_XREG_RFIRQM0 0x4008868C /**< RF interrupt masks */
80 #define RFCORE_XREG_RFIRQM1 0x40088690 /**< RF interrupt masks */
81 #define RFCORE_XREG_RFERRM 0x40088694 /**< RF error interrupt mask */
82 #define RFCORE_XREG_D18_SPARE_OPAMPMC 0x40088698 /**< Operational amp mode ctrl */
83 #define RFCORE_XREG_RFRND 0x4008869C /**< Random data */
84 #define RFCORE_XREG_MDMCTRL0 0x400886A0 /**< Controls modem */
85 #define RFCORE_XREG_MDMCTRL1 0x400886A4 /**< Controls modem */
86 #define RFCORE_XREG_FREQEST 0x400886A8 /**< Estimated RF frequency offset */
87 #define RFCORE_XREG_RXCTRL 0x400886AC /**< Tune receive section */
88 #define RFCORE_XREG_FSCTRL 0x400886B0 /**< Tune frequency synthesizer */
89 #define RFCORE_XREG_FSCAL1 0x400886B8 /**< Tune frequency calibration */
90 #define RFCORE_XREG_FSCAL2 0x400886BC /**< Tune frequency calibration */
91 #define RFCORE_XREG_FSCAL3 0x400886C0 /**< Tune frequency calibration */
92 #define RFCORE_XREG_AGCCTRL0 0x400886C4 /**< AGC dynamic range control */
93 #define RFCORE_XREG_AGCCTRL1 0x400886C8 /**< AGC reference level */
94 #define RFCORE_XREG_AGCCTRL2 0x400886CC /**< AGC gain override */
95 #define RFCORE_XREG_AGCCTRL3 0x400886D0 /**< AGC control */
96 #define RFCORE_XREG_ADCTEST0 0x400886D4 /**< ADC tuning */
97 #define RFCORE_XREG_ADCTEST1 0x400886D8 /**< ADC tuning */
98 #define RFCORE_XREG_ADCTEST2 0x400886DC /**< ADC tuning */
99 #define RFCORE_XREG_MDMTEST0 0x400886E0 /**< Test register for modem */
100 #define RFCORE_XREG_MDMTEST1 0x400886E4 /**< Test Register for Modem */
101 #define RFCORE_XREG_DACTEST0 0x400886E8 /**< DAC override value */
102 #define RFCORE_XREG_DACTEST1 0x400886EC /**< DAC override value */
103 #define RFCORE_XREG_DACTEST2 0x400886F0 /**< DAC test setting */
104 #define RFCORE_XREG_ATEST 0x400886F4 /**< Analog test control */
105 #define RFCORE_XREG_PTEST0 0x400886F8 /**< Override power-down register */
106 #define RFCORE_XREG_PTEST1 0x400886FC /**< Override power-down register */
107 #define RFCORE_XREG_CSPPROG0 0x40088700 /**< CSP program */
108 #define RFCORE_XREG_CSPPROG1 0x40088704 /**< CSP program */
109 #define RFCORE_XREG_CSPPROG2 0x40088708 /**< CSP program */
110 #define RFCORE_XREG_CSPPROG3 0x4008870C /**< CSP program */
111 #define RFCORE_XREG_CSPPROG4 0x40088710 /**< CSP program */
112 #define RFCORE_XREG_CSPPROG5 0x40088714 /**< CSP program */
113 #define RFCORE_XREG_CSPPROG6 0x40088718 /**< CSP program */
114 #define RFCORE_XREG_CSPPROG7 0x4008871C /**< CSP program */
115 #define RFCORE_XREG_CSPPROG8 0x40088720 /**< CSP program */
116 #define RFCORE_XREG_CSPPROG9 0x40088724 /**< CSP program */
117 #define RFCORE_XREG_CSPPROG10 0x40088728 /**< CSP program */
118 #define RFCORE_XREG_CSPPROG11 0x4008872C /**< CSP program */
119 #define RFCORE_XREG_CSPPROG12 0x40088730 /**< CSP program */
120 #define RFCORE_XREG_CSPPROG13 0x40088734 /**< CSP program */
121 #define RFCORE_XREG_CSPPROG14 0x40088738 /**< CSP program */
122 #define RFCORE_XREG_CSPPROG15 0x4008873C /**< CSP program */
123 #define RFCORE_XREG_CSPPROG16 0x40088740 /**< CSP program */
124 #define RFCORE_XREG_CSPPROG17 0x40088744 /**< CSP program */
125 #define RFCORE_XREG_CSPPROG18 0x40088748 /**< CSP program */
126 #define RFCORE_XREG_CSPPROG19 0x4008874C /**< CSP program */
127 #define RFCORE_XREG_CSPPROG20 0x40088750 /**< CSP program */
128 #define RFCORE_XREG_CSPPROG21 0x40088754 /**< CSP program */
129 #define RFCORE_XREG_CSPPROG22 0x40088758 /**< CSP program */
130 #define RFCORE_XREG_CSPPROG23 0x4008875C /**< CSP program */
131 #define RFCORE_XREG_CSPCTRL 0x40088780 /**< CSP control bit */
132 #define RFCORE_XREG_CSPSTAT 0x40088784 /**< CSP status register */
133 #define RFCORE_XREG_CSPX 0x40088788 /**< CSP X data register */
134 #define RFCORE_XREG_CSPY 0x4008878C /**< CSP Y data register */
135 #define RFCORE_XREG_CSPZ 0x40088790 /**< CSP Z data register */
136 #define RFCORE_XREG_CSPT 0x40088794 /**< CSP T data register */
137 #define RFCORE_XREG_RFC_DUTY_CYCLE 0x400887A0 /**< RX duty cycle control */
138 #define RFCORE_XREG_RFC_OBS_CTRL0 0x400887AC /**< RF observation mux control */
139 #define RFCORE_XREG_RFC_OBS_CTRL1 0x400887B0 /**< RF observation mux control */
140 #define RFCORE_XREG_RFC_OBS_CTRL2 0x400887B4 /**< RF observation mux control */
141 #define RFCORE_XREG_TXFILTCFG 0x400887E8 /**< TX filter configuration */
142 /** @} */
143 /*---------------------------------------------------------------------------*/
144 /** \name RFCORE_XREG_FRMFILT0 register offsets
145  * @{
146  */
147 #define RFCORE_XREG_FRMFILT0_MAX_FRAME_VERSION 0x0000000C /**< Frame version filtering */
148 #define RFCORE_XREG_FRMFILT0_PAN_COORDINATOR 0x00000002 /**< PAN coordinator */
149 #define RFCORE_XREG_FRMFILT0_FRAME_FILTER_EN 0x00000001 /**< Enables frame filtering */
150 /** @} */
151 /*---------------------------------------------------------------------------*/
152 /** \name RFCORE_XREG_FRMFILT1 register offsets
153  * @{
154  */
155 #define RFCORE_XREG_FRMFILT1_ACCEPT_FT_3_MAC_CMD 0x00000040 /**< MAC command frame filt */
156 #define RFCORE_XREG_FRMFILT1_ACCEPT_FT_2_ACK 0x00000020 /**< ack frame filt */
157 #define RFCORE_XREG_FRMFILT1_ACCEPT_FT_1_DATA 0x00000010 /**< data frame filt */
158 #define RFCORE_XREG_FRMFILT1_ACCEPT_FT_0_BEACON 0x00000008 /**< beacon frame filt */
159 #define RFCORE_XREG_FRMFILT1_MODIFY_FT_FILTER 0x00000006 /**< Frame type modify */
160 /** @} */
161 /*---------------------------------------------------------------------------*/
162 /** \name RFCORE_XREG_SRCMATCH register bit masks
163  * @{
164  */
165 #define RFCORE_XREG_SRCMATCH_PEND_DATAREQ_ONLY 0x00000004 /**< AUTOPEND function */
166 #define RFCORE_XREG_SRCMATCH_AUTOPEND 0x00000002 /**< Automatic acknowledgment */
167 #define RFCORE_XREG_SRCMATCH_SRC_MATCH_EN 0x00000001 /**< Source address matching enable */
168 /** @} */
169 /*---------------------------------------------------------------------------*/
170 /** \name RFCORE_XREG_SRCSHORTEN0 register bit masks
171  * @{
172  */
173 #define RFCORE_XREG_SRCSHORTEN0_SHORT_ADDR_EN 0x000000FF /**< SHORT_ADDR_EN[7:0] */
174 /** @} */
175 /*---------------------------------------------------------------------------*/
176 /** \name RFCORE_XREG_SRCSHORTEN1 register bit masks
177  * @{
178  */
179 #define RFCORE_XREG_SRCSHORTEN1_SHORT_ADDR_EN 0x000000FF /**< SHORT_ADDR_EN[15:8] */
180 /** @} */
181 /*---------------------------------------------------------------------------*/
182 /** \name RFCORE_XREG_SRCSHORTEN2 register bit masks
183  * @{
184  */
185 #define RFCORE_XREG_SRCSHORTEN2_SHORT_ADDR_EN 0x000000FF /**< SHORT_ADDR_EN[23:16] */
186 /** @} */
187 /*---------------------------------------------------------------------------*/
188 /** \name RFCORE_XREG_SRCEXTEN0 register bit masks
189  * @{
190  */
191 #define RFCORE_XREG_SRCEXTEN0_EXT_ADDR_EN 0x000000FF /**< EXT_ADDR_EN[7:0] */
192 /** @} */
193 /*---------------------------------------------------------------------------*/
194 /** \name RFCORE_XREG_SRCEXTEN1 register bit masks
195  * @{
196  */
197 #define RFCORE_XREG_SRCEXTEN1_EXT_ADDR_EN 0x000000FF /**< EXT_ADDR_EN[15:8] */
198 /** @} */
199 /*---------------------------------------------------------------------------*/
200 /** \name RFCORE_XREG_SRCEXTEN2 register bit masks
201  * @{
202  */
203 #define RFCORE_XREG_SRCEXTEN2_EXT_ADDR_EN 0x000000FF /**< EXT_ADDR_EN[23:16] */
204 /** @} */
205 /*---------------------------------------------------------------------------*/
206 /** \name RFCORE_XREG_FRMCTRL0 register bit masks
207  * @{
208  */
209 #define RFCORE_XREG_FRMCTRL0_APPEND_DATA_MODE 0x00000080 /**< Append data mode */
210 #define RFCORE_XREG_FRMCTRL0_AUTOCRC 0x00000040 /**< Auto CRC generation / checking */
211 #define RFCORE_XREG_FRMCTRL0_AUTOACK 0x00000020 /**< Transmit ACK frame enable */
212 #define RFCORE_XREG_FRMCTRL0_ENERGY_SCAN 0x00000010 /**< RSSI register content control */
213 #define RFCORE_XREG_FRMCTRL0_RX_MODE 0x0000000C /**< Set RX modes */
214 #define RFCORE_XREG_FRMCTRL0_TX_MODE 0x00000003 /**< Set test modes for TX */
215 /** @} */
216 /*---------------------------------------------------------------------------*/
217 /** \name RFCORE_XREG_FRMCTRL1 register bit masks
218  * @{
219  */
220 #define RFCORE_XREG_FRMCTRL1_PENDING_OR 0x00000004 /**< Pending data bit control */
221 #define RFCORE_XREG_FRMCTRL1_IGNORE_TX_UNDERF 0x00000002 /**< TX underflow ignore */
222 #define RFCORE_XREG_FRMCTRL1_SET_RXENMASK_ON_TX 0x00000001 /**< RXENABLE control */
223 /** @} */
224 /*---------------------------------------------------------------------------*/
225 /** \name RFCORE_XREG_RXENABLE register bit masks
226  * @{
227  */
228 #define RFCORE_XREG_RXENABLE_RXENMASK 0x000000FF /**< Enables the receiver. */
229 /** @} */
230 /*---------------------------------------------------------------------------*/
231 /** \name RFCORE_XREG_RXMASKSET register bit masks
232  * @{
233  */
234 #define RFCORE_XREG_RXMASKSET_RXENMASKSET 0x000000FF /**< Write to RXENMASK (OR) */
235 /** @} */
236 /*---------------------------------------------------------------------------*/
237 /** \name RFCORE_XREG_RXMASKCLR register bit masks
238  * @{
239  */
240 #define RFCORE_XREG_RXMASKCLR_RXENMASKCLR 0x000000FF /**< RXENMASK clear bits */
241 /** @} */
242 /*---------------------------------------------------------------------------*/
243 /** \name RFCORE_XREG_FREQTUNE register bit masks
244  * @{
245  */
246 #define RFCORE_XREG_FREQTUNE_XOSC32M_TUNE 0x0000000F /**< Tune crystal oscillator */
247 /** @} */
248 /*---------------------------------------------------------------------------*/
249 /** \name RFCORE_XREG_FREQCTRL register bit masks
250  * @{
251  */
252 #define RFCORE_XREG_FREQCTRL_FREQ 0x0000007F /**< Frequency control word */
253 /** @} */
254 /*---------------------------------------------------------------------------*/
255 /** \name RFCORE_XREG_TXPOWER register bit masks
256  * @{
257  */
258 #define RFCORE_XREG_TXPOWER_PA_POWER 0x000000F0 /**< PA power control */
259 #define RFCORE_XREG_TXPOWER_PA_BIAS 0x0000000F /**< PA bias control */
260 /** @} */
261 /*---------------------------------------------------------------------------*/
262 /** \name RFCORE_XREG_TXCTRL register bit masks
263  * @{
264  */
265 #define RFCORE_XREG_TXCTRL_DAC_CURR 0x00000070 /**< Change the current in the DAC. */
266 #define RFCORE_XREG_TXCTRL_DAC_DC 0x0000000C /**< Adjusts the DC level to the TX mixer */
267 #define RFCORE_XREG_TXCTRL_TXMIX_CURRENT 0x00000003 /**< TX mixer core current */
268 /** @} */
269 /*---------------------------------------------------------------------------*/
270 /** \name RFCORE_XREG_FSMSTAT0 register bit masks
271  * @{
272  */
273 #define RFCORE_XREG_FSMSTAT0_CAL_DONE 0x00000080 /**< Calib has been performed */
274 #define RFCORE_XREG_FSMSTAT0_CAL_RUNNING 0x00000040 /**< Calib status */
275 #define RFCORE_XREG_FSMSTAT0_FSM_FFCTRL_STATE 0x0000003F /**< FIFO and FFCTRL status */
276 /** @} */
277 /*---------------------------------------------------------------------------*/
278 /** \name RFCORE_XREG_FSMSTAT1 register bit masks
279  * @{
280  */
281 #define RFCORE_XREG_FSMSTAT1_FIFO 0x00000080 /**< FIFO status */
282 #define RFCORE_XREG_FSMSTAT1_FIFOP 0x00000040 /**< FIFOP status */
283 #define RFCORE_XREG_FSMSTAT1_SFD 0x00000020 /**< SFD was sent/received */
284 #define RFCORE_XREG_FSMSTAT1_CCA 0x00000010 /**< Clear channel assessment */
285 #define RFCORE_XREG_FSMSTAT1_SAMPLED_CCA 0x00000008 /**< CCA sample value */
286 #define RFCORE_XREG_FSMSTAT1_LOCK_STATUS 0x00000004 /**< PLL lock status */
287 #define RFCORE_XREG_FSMSTAT1_TX_ACTIVE 0x00000002 /**< Status signal - TX states */
288 #define RFCORE_XREG_FSMSTAT1_RX_ACTIVE 0x00000001 /**< Status signal - RX states */
289 /** @} */
290 /*---------------------------------------------------------------------------*/
291 /** \name RFCORE_XREG_FIFOPCTRL register bit masks
292  * @{
293  */
294 #define RFCORE_XREG_FIFOPCTRL_FIFOP_THR 0x0000007F /**< FIFOP signal threshold */
295 /** @} */
296 /*---------------------------------------------------------------------------*/
297 /** \name RFCORE_XREG_FSMCTRL register bit masks
298  * @{
299  */
300 #define RFCORE_XREG_FSMCTRL_SLOTTED_ACK 0x00000002 /**< ACK frame TX timing */
301 #define RFCORE_XREG_FSMCTRL_RX2RX_TIME_OFF 0x00000001 /**< 12-sym timeout after RX */
302 /** @} */
303 /*---------------------------------------------------------------------------*/
304 /** \name RFCORE_XREG_CCACTRL0 register bit masks
305  * @{
306  */
307 #define RFCORE_XREG_CCACTRL0_CCA_THR 0x000000FF /**< Clear-channel-assessment */
308 /** @} */
309 /*---------------------------------------------------------------------------*/
310 /** \name RFCORE_XREG_CCACTRL1 register bit masks
311  * @{
312  */
313 #define RFCORE_XREG_CCACTRL1_CCA_MODE 0x00000018 /**< CCA mode */
314 #define RFCORE_XREG_CCACTRL1_CCA_HYST 0x00000007 /**< CCA hysteresis */
315 /** @} */
316 /*---------------------------------------------------------------------------*/
317 /** \name RFCORE_XREG_RSSI register bit masks
318  * @{
319  */
320 #define RFCORE_XREG_RSSI_RSSI_VAL 0x000000FF /**< RSSI estimate */
321 #define RFCORE_XREG_RSSI_RSSI_VAL_S 0
322 /** @} */
323 /*---------------------------------------------------------------------------*/
324 /** \name RFCORE_XREG_RSSISTAT register bit masks
325  * @{
326  */
327 #define RFCORE_XREG_RSSISTAT_RSSI_VALID 0x00000001 /**< RSSI value is valid */
328 /** @} */
329 /*---------------------------------------------------------------------------*/
330 /** \name RFCORE_XREG_RXFIRST register bit masks
331  * @{
332  */
333 #define RFCORE_XREG_RXFIRST_DATA 0x000000FF /**< First byte of the RX FIFO */
334 /** @} */
335 /*---------------------------------------------------------------------------*/
336 /** \name RFCORE_XREG_RXFIFOCNT register bit masks
337  * @{
338  */
339 #define RFCORE_XREG_RXFIFOCNT_RXFIFOCNT 0x000000FF /**< Number of bytes in the RX FIFO */
340 /** @} */
341 /*---------------------------------------------------------------------------*/
342 /** \name RFCORE_XREG_TXFIFOCNT register bit masks
343  * @{
344  */
345 #define RFCORE_XREG_TXFIFOCNT_TXFIFOCNT 0x000000FF /**< Number of bytes in the TX FIFO */
346 /** @} */
347 /*---------------------------------------------------------------------------*/
348 /** \name RX FIFO pointers
349  * @{
350  */
351 #define RFCORE_XREG_RXFIRST_PTR_RXFIRST_PTR 0x000000FF /**< Byte 1 */
352 #define RFCORE_XREG_RXLAST_PTR_RXLAST_PTR 0x000000FF /**< Last byte + 1 */
353 #define RFCORE_XREG_RXP1_PTR_RXP1_PTR 0x000000FF /**< Frame 1, byte 1 */
354 #define RFCORE_XREG_RXP2_PTR_RXP2_PTR 0x000000FF /**< Last frame, byte 1 */
355 /** @} */
356 /*---------------------------------------------------------------------------*/
357 /** \name TX FIFO pointers
358  * @{
359  */
360 #define RFCORE_XREG_TXFIRST_PTR_TXFIRST_PTR 0x000000FF /**< Next byte to be TXd */
361 #define RFCORE_XREG_TXLAST_PTR_TXLAST_PTR 0x000000FF /**< Last byte + 1 */
362 /** @} */
363 /*---------------------------------------------------------------------------*/
364 /** \name RFCORE_XREG_RFIRQM0 register bit masks
365  * @{
366  */
367 #define RFCORE_XREG_RFIRQM0_RFIRQM 0x000000FF /**< Interrupt source bit mask */
368 #define RFCORE_XREG_RFIRQM0_RXMASKZERO 0x00000080 /**< RXENABLE gone all-zero */
369 #define RFCORE_XREG_RFIRQM0_RXPKTDONE 0x00000040 /**< Complete frame RX */
370 #define RFCORE_XREG_RFIRQM0_FRAME_ACCEPTED 0x00000020 /**< Frame has passed frame filter */
371 #define RFCORE_XREG_RFIRQM0_SRC_MATCH_FOUND 0x00000010 /**< Source match is found */
372 #define RFCORE_XREG_RFIRQM0_SRC_MATCH_DONE 0x00000008 /**< Source matching is complete */
373 #define RFCORE_XREG_RFIRQM0_FIFOP 0x00000004 /**< RX FIFO exceeded threshold */
374 #define RFCORE_XREG_RFIRQM0_SFD 0x00000002 /**< SFD TX or RX */
375 #define RFCORE_XREG_RFIRQM0_ACT_UNUSED 0x00000001 /**< Reserved */
376 /** @} */
377 /*---------------------------------------------------------------------------*/
378 /** \name RFCORE_XREG_RFIRQM1 register bit masks
379  * @{
380  */
381 #define RFCORE_XREG_RFIRQM1_RFIRQM 0x0000003F /**< Interrupt source bit mask */
382 #define RFCORE_XREG_RFIRQM1_CSP_WAIT 0x00000020 /**< CSP Execution continued */
383 #define RFCORE_XREG_RFIRQM1_CSP_STOP 0x00000010 /**< CSP has stopped program */
384 #define RFCORE_XREG_RFIRQM1_CSP_MANINT 0x00000008 /**< CSP Manual interrupt */
385 #define RFCORE_XREG_RFIRQM1_RFIDLE 0x00000004 /**< IDLE state entered */
386 #define RFCORE_XREG_RFIRQM1_TXDONE 0x00000002 /**< Complete frame TX finished */
387 #define RFCORE_XREG_RFIRQM1_TXACKDONE 0x00000001 /**< ACK frame TX finished */
388 /** @} */
389 /*---------------------------------------------------------------------------*/
390 /** \name RFCORE_XREG_RFERRM register bit masks
391  * @{
392  */
393 #define RFCORE_XREG_RFERRM_RFERRM 0x0000007F /**< RF error interrupt mask */
394 #define RFCORE_XREG_RFERRM_STROBEERR 0x00000040 /**< Strobe error */
395 #define RFCORE_XREG_RFERRM_TXUNDERF 0x00000020 /**< TX FIFO underflowed */
396 #define RFCORE_XREG_RFERRM_TXOVERF 0x00000010 /**< TX FIFO overflowed */
397 #define RFCORE_XREG_RFERRM_RXUNDERF 0x00000008 /**< RX FIFO underflowed */
398 #define RFCORE_XREG_RFERRM_RXOVERF 0x00000004 /**< RX FIFO overflowed */
399 #define RFCORE_XREG_RFERRM_RXABO 0x00000002 /**< Frame RX was aborted */
400 #define RFCORE_XREG_RFERRM_NLOCK 0x00000001 /**< Frequency synthesizer lock error */
401 /** @} */
402 /*---------------------------------------------------------------------------*/
403 /** \name RFCORE_XREG_D18_SPARE_OPAMPMC register bit masks
404  * @{
405  */
406 #define RFCORE_XREG_D18_SPARE_OPAMPMC_MODE 0x00000003 /**< Operational amplifier mode */
407 /** @} */
408 /*---------------------------------------------------------------------------*/
409 /** \name RFCORE_XREG_RFRND register bit masks
410  * @{
411  */
412 #define RFCORE_XREG_RFRND_QRND 0x00000002 /**< Random bit from the Q channel */
413 #define RFCORE_XREG_RFRND_IRND 0x00000001 /**< Random bit from the I channel */
414 /** @} */
415 /*---------------------------------------------------------------------------*/
416 /** \name RFCORE_XREG_MDMCTRL0 register bit masks
417  * @{
418  */
419 #define RFCORE_XREG_MDMCTRL0_DEM_NUM_ZEROS 0x000000C0 /**< Num of zero symbols before sync word */
420 #define RFCORE_XREG_MDMCTRL0_DEMOD_AVG_MODE 0x00000020 /**< Frequency offset averaging filter */
421 #define RFCORE_XREG_MDMCTRL0_PREAMBLE_LENGTH 0x0000001E /**< Number of preamble bytes */
422 #define RFCORE_XREG_MDMCTRL0_TX_FILTER 0x00000001 /**< TX filter type */
423 /** @} */
424 /*---------------------------------------------------------------------------*/
425 /** \name RFCORE_XREG_MDMCTRL1 register bit masks
426  * @{
427  */
428 #define RFCORE_XREG_MDMCTRL1_CORR_THR_SFD 0x00000020 /**< SFD detection requirements */
429 #define RFCORE_XREG_MDMCTRL1_CORR_THR 0x0000001F /**< Demodulator correlator threshold */
430 /** @} */
431 /*---------------------------------------------------------------------------*/
432 /** \name RFCORE_XREG_FREQEST register bit masks
433  * @{
434  */
435 #define RFCORE_XREG_FREQEST_FREQEST 0x000000FF
436 /** @} */
437 /*---------------------------------------------------------------------------*/
438 /** \name RFCORE_XREG_RXCTRL register bit masks
439  * @{
440  */
441 #define RFCORE_XREG_RXCTRL_GBIAS_LNA2_REF 0x00000030 /**< LNA2/mixer PTAT current output */
442 #define RFCORE_XREG_RXCTRL_GBIAS_LNA_REF 0x0000000C /**< LNA PTAT current output */
443 #define RFCORE_XREG_RXCTRL_MIX_CURRENT 0x00000003 /**< Control of the output current */
444 /** @} */
445 /*---------------------------------------------------------------------------*/
446 /** \name RFCORE_XREG_FSCTRL register bit masks
447  * @{
448  */
449 #define RFCORE_XREG_FSCTRL_PRE_CURRENT 0x000000C0 /**< Prescaler current setting */
450 #define RFCORE_XREG_FSCTRL_LODIV_BUF_CURRENT_TX 0x00000030 /**< Adjusts current in mixer and PA adjust */
451 #define RFCORE_XREG_FSCTRL_LODIV_BUF_CURRENT_RX 0x0000000C /**< Adjusts current in mixer and PA adjust */
452 #define RFCORE_XREG_FSCTRL_LODIV_CURRENT 0x00000003 /**< Adjusts divider currents */
453 /** @} */
454 /*---------------------------------------------------------------------------*/
455 /** \name RFCORE_XREG_FSCAL1 register bit masks
456  * @{
457  */
458 #define RFCORE_XREG_FSCAL1_VCO_CURR_CAL_OE 0x00000080 /**< Override current calibration */
459 #define RFCORE_XREG_FSCAL1_VCO_CURR_CAL 0x0000007C /**< Calibration result */
460 #define RFCORE_XREG_FSCAL1_VCO_CURR 0x00000003 /**< Defines current in VCO core */
461 /** @} */
462 /*---------------------------------------------------------------------------*/
463 /** \name RFCORE_XREG_FSCAL2 register bit masks
464  * @{
465  */
466 #define RFCORE_XREG_FSCAL2_VCO_CAPARR_OE 0x00000040 /**< Override the calibration result */
467 #define RFCORE_XREG_FSCAL2_VCO_CAPARR 0x0000003F /**< VCO capacitor array setting */
468 /** @} */
469 /*---------------------------------------------------------------------------*/
470 /** \name RFCORE_XREG_FSCAL3 register bit masks
471  * @{
472  */
473 #define RFCORE_XREG_FSCAL3_VCO_DAC_EN_OV 0x00000040 /**< VCO DAC Enable */
474 #define RFCORE_XREG_FSCAL3_VCO_VC_DAC 0x0000003C /**< Varactor control voltage Bit vector */
475 #define RFCORE_XREG_FSCAL3_VCO_CAPARR_CAL_CTRL 0x00000003 /**< Calibration accuracy setting */
476 /** @} */
477 /*---------------------------------------------------------------------------*/
478 /** \name RFCORE_XREG_AGCCTRL0 register bit masks
479  * @{
480  */
481 #define RFCORE_XREG_AGCCTRL0_AGC_DR_XTND_EN 0x00000040 /**< AAF attenuation adjustment */
482 #define RFCORE_XREG_AGCCTRL0_AGC_DR_XTND_THR 0x0000003F /**< Enable extra attenuation in front end */
483 /** @} */
484 /*---------------------------------------------------------------------------*/
485 /** \name RFCORE_XREG_AGCCTRL1 register bit masks
486  * @{
487  */
488 #define RFCORE_XREG_AGCCTRL1_AGC_REF 0x0000003F /**< Target value for the AGC control loop */
489 /** @} */
490 /*---------------------------------------------------------------------------*/
491 /** \name RFCORE_XREG_AGCCTRL2 register bit masks
492  * @{
493  */
494 #define RFCORE_XREG_AGCCTRL2_LNA1_CURRENT 0x000000C0 /**< Overrride value for LNA 1 */
495 #define RFCORE_XREG_AGCCTRL2_LNA2_CURRENT 0x00000038 /**< Overrride value for LNA 2 */
496 #define RFCORE_XREG_AGCCTRL2_LNA3_CURRENT 0x00000006 /**< Overrride value for LNA 3 */
497 #define RFCORE_XREG_AGCCTRL2_LNA_CURRENT_OE 0x00000001 /**< AGC LNA override */
498 /** @} */
499 /*---------------------------------------------------------------------------*/
500 /** \name RFCORE_XREG_AGCCTRL3 register bit masks
501  * @{
502  */
503 #define RFCORE_XREG_AGCCTRL3_AGC_SETTLE_WAIT 0x00000060 /**< AGC analog gain wait */
504 #define RFCORE_XREG_AGCCTRL3_AGC_WIN_SIZE 0x00000018 /**< AGC accumulate-and-dump window size */
505 #define RFCORE_XREG_AGCCTRL3_AAF_RP 0x00000006 /**< AGC to AAF control signal override */
506 #define RFCORE_XREG_AGCCTRL3_AAF_RP_OE 0x00000001 /**< AAF control signal override */
507 /** @} */
508 /*---------------------------------------------------------------------------*/
509 /** \name RFCORE_XREG_ADCTEST0 register bit masks
510  * @{
511  */
512 #define RFCORE_XREG_ADCTEST0_ADC_VREF_ADJ 0x000000C0 /**< Quantizer threshold control */
513 #define RFCORE_XREG_ADCTEST0_ADC_QUANT_ADJ 0x00000030 /**< Quantizer threshold control */
514 #define RFCORE_XREG_ADCTEST0_ADC_GM_ADJ 0x0000000E /**< Gm-control for test and debug */
515 #define RFCORE_XREG_ADCTEST0_ADC_DAC2_EN 0x00000001 /**< Enables DAC2 */
516 /** @} */
517 /*---------------------------------------------------------------------------*/
518 /** \name RFCORE_XREG_ADCTEST1 register bit masks
519  * @{
520  */
521 #define RFCORE_XREG_ADCTEST1_ADC_TEST_CTRL 0x000000F0 /**< ADC test mode selector */
522 #define RFCORE_XREG_ADCTEST1_ADC_C2_ADJ 0x0000000C /**< ADC capacitor value adjust */
523 #define RFCORE_XREG_ADCTEST1_ADC_C3_ADJ 0x00000003 /**< ADC capacitor value adjust */
524 /** @} */
525 /*---------------------------------------------------------------------------*/
526 /** \name RFCORE_XREG_ADCTEST2 register bit masks
527  * @{
528  */
529 #define RFCORE_XREG_ADCTEST2_ADC_TEST_MODE 0x00000060 /**< ADC data output test mode */
530 #define RFCORE_XREG_ADCTEST2_AAF_RS 0x00000018 /**< AAF series resistance control */
531 #define RFCORE_XREG_ADCTEST2_ADC_FF_ADJ 0x00000006 /**< Adjust feed forward */
532 #define RFCORE_XREG_ADCTEST2_ADC_DAC_ROT 0x00000001 /**< Control of DAC DWA scheme */
533 /** @} */
534 /*---------------------------------------------------------------------------*/
535 /** \name RFCORE_XREG_MDMTEST0 register bit masks
536  * @{
537  */
538 #define RFCORE_XREG_MDMTEST0_TX_TONE 0x000000F0 /**< Baseband tone TX enable */
539 #define RFCORE_XREG_MDMTEST0_DC_WIN_SIZE 0x0000000C /**< Controls the numbers of samples */
540 #define RFCORE_XREG_MDMTEST0_DC_BLOCK_MODE 0x00000003 /**< Mode of operation select */
541 /** @} */
542 /*---------------------------------------------------------------------------*/
543 /** \name RFCORE_XREG_MDMTEST1 register bit masks
544  * @{
545  */
546 #define RFCORE_XREG_MDMTEST1_USEMIRROR_IF 0x00000020 /**< IF frequency select */
547 #define RFCORE_XREG_MDMTEST1_MOD_IF 0x00000010 /**< Modulation select */
548 #define RFCORE_XREG_MDMTEST1_RAMP_AMP 0x00000008 /**< Ramping of DAC output enable */
549 #define RFCORE_XREG_MDMTEST1_RFC_SNIFF_EN 0x00000004 /**< Packet sniffer module enable */
550 #define RFCORE_XREG_MDMTEST1_MODULATION_MODE 0x00000002 /**< RF-modulation mode */
551 #define RFCORE_XREG_MDMTEST1_LOOPBACK_EN 0x00000001 /**< Modulated data loopback enable */
552 /** @} */
553 /*---------------------------------------------------------------------------*/
554 /** \name RFCORE_XREG_DACTEST0 register bit masks
555  * @{
556  */
557 #define RFCORE_XREG_DACTEST0_DAC_Q 0x400886FF /**< Q-branch DAC override value */
558 /** @} */
559 /*---------------------------------------------------------------------------*/
560 /** \name RFCORE_XREG_DACTEST1 register bit masks
561  * @{
562  */
563 #define RFCORE_XREG_DACTEST1_DAC_I 0x400886FF /**< I-branch DAC override value */
564 /** @} */
565 /*---------------------------------------------------------------------------*/
566 /** \name RFCORE_XREG_DACTEST2 register bit masks
567  * @{
568  */
569 #define RFCORE_XREG_DACTEST2_DAC_DEM_EN 0x00000020 /**< Dynamic element matching enable */
570 #define RFCORE_XREG_DACTEST2_DAC_CASC_CTRL 0x00000018 /**< Adjustment of output stage */
571 #define RFCORE_XREG_DACTEST2_DAC_SRC 0x00000007 /**< TX DAC data src select */
572 /** @} */
573 /*---------------------------------------------------------------------------*/
574 /** \name RFCORE_XREG_ATEST register bit masks
575  * @{
576  */
577 #define RFCORE_XREG_ATEST_ATEST_CTRL 0x0000003F /**< Controls the analog test mode */
578 #define RFCORE_XREG_ATEST_ATEST_CTRL_DIS 0x00000000 /**< Analog test mode: disabled */
579 #define RFCORE_XREG_ATEST_ATEST_CTRL_TEMP 0x00000001 /**< Analog test mode: enable temperature sensor */
580 /** @} */
581 /*---------------------------------------------------------------------------*/
582 /** \name RFCORE_XREG_PTEST0 register bit masks
583  * @{
584  */
585 #define RFCORE_XREG_PTEST0_PRE_PD 0x00000080 /**< Prescaler power-down signal */
586 #define RFCORE_XREG_PTEST0_CHP_PD 0x00000040 /**< Charge pump power-down signal */
587 #define RFCORE_XREG_PTEST0_ADC_PD 0x00000020 /**< ADC power-down signal When */
588 #define RFCORE_XREG_PTEST0_DAC_PD 0x00000010 /**< DAC power-down signal When */
589 #define RFCORE_XREG_PTEST0_LNA_PD 0x0000000C /**< Low-noise amplifier power-down */
590 #define RFCORE_XREG_PTEST0_TXMIX_PD 0x00000002 /**< Transmit mixer power-down */
591 #define RFCORE_XREG_PTEST0_AAF_PD 0x00000001 /**< Antialiasing filter power-down */
592 /** @} */
593 /*---------------------------------------------------------------------------*/
594 /** \name RFCORE_XREG_PTEST1 register bit masks
595  * @{
596  */
597 #define RFCORE_XREG_PTEST1_PD_OVERRIDE 0x00000008 /**< Override module enabling and disabling */
598 #define RFCORE_XREG_PTEST1_PA_PD 0x00000004 /**< Power amplifier power-down signal */
599 #define RFCORE_XREG_PTEST1_VCO_PD 0x00000002 /**< VCO power-down signal */
600 #define RFCORE_XREG_PTEST1_LODIV_PD 0x00000001 /**< LO power-down signal */
601 /** @} */
602 /*---------------------------------------------------------------------------*/
603 /** \name RFCORE_XREG_CSPPROG[0:24] register bit masks
604  * @{
605  */
606 #define RFCORE_XREG_CSPPROG_CSP_INSTR 0x000000FF /**< Byte N of the CSP program */
607 /** @} */
608 /*---------------------------------------------------------------------------*/
609 /** \name RFCORE_XREG_CSPCTRL register bit masks
610  * @{
611  */
612 #define RFCORE_XREG_CSPCTRL_MCU_CTRL 0x00000001 /**< CSP MCU control input */
613 /** @} */
614 /*---------------------------------------------------------------------------*/
615 /** \name RFCORE_XREG_CSPSTAT register bit masks
616  * @{
617  */
618 #define RFCORE_XREG_CSPSTAT_CSP_RUNNING 0x00000020 /**< CSP Running / Idle */
619 #define RFCORE_XREG_CSPSTAT_CSP_PC 0x0000001F /**< CSP program counter */
620 /** @} */
621 /*---------------------------------------------------------------------------*/
622 /** \name RFCORE_XREG_CSPX register bit masks
623  * @{
624  */
625 #define RFCORE_XREG_CSPX_CSPX 0x000000FF /**< CSP X data */
626 /** @} */
627 /*---------------------------------------------------------------------------*/
628 /** \name RFCORE_XREG_CSPY register bit masks
629  * @{
630  */
631 #define RFCORE_XREG_CSPY_CSPY 0x000000FF /**< CSP Y data */
632 /** @} */
633 /*---------------------------------------------------------------------------*/
634 /** \name RFCORE_XREG_CSPZ register bit masks
635  * @{
636  */
637 #define RFCORE_XREG_CSPZ_CSPZ 0x000000FF /**< CSP Z data */
638 /** @} */
639 /*---------------------------------------------------------------------------*/
640 /** \name RFCORE_XREG_CSPT register bit masks
641  * @{
642  */
643 #define RFCORE_XREG_CSPT_CSPT 0x000000FF /**< CSP T data */
644 /** @} */
645 /*---------------------------------------------------------------------------*/
646 /** \name RFCORE_XREG_RFC_DUTY_CYCLE register bit masks
647  * @{
648  */
649 #define RFCORE_XREG_RFC_DUTY_CYCLE_SWD_EN 0x00000040 /**< Wire debug mode */
650 #define RFCORE_XREG_RFC_DUTY_CYCLE_DTC_DCCAL_MODE 0x00000030 /**< Periodic DC-recalibration mode */
651 #define RFCORE_XREG_RFC_DUTY_CYCLE_DUTYCYCLE_CNF 0x0000000E /**< Defines duty cycling */
652 #define RFCORE_XREG_RFC_DUTY_CYCLE_DUTYCYCLE_EN 0x00000001 /**< Duty cycling mode enable */
653 /** @} */
654 /*---------------------------------------------------------------------------*/
655 /** \name RFCORE_XREG_RFC_OBS_CTRL[0:2] register bit masks
656  * @{
657  */
658 #define RFCORE_XREG_RFC_OBS_CTRL0_RFC_OBS_POL0 0x00000040 /**< RFC_OBS_MUX0 XOR bit */
659 #define RFCORE_XREG_RFC_OBS_CTRL0_RFC_OBS_MUX0 0x0000003F /**< RF Core MUX out control */
660 #define RFCORE_XREG_RFC_OBS_CTRL1_RFC_OBS_POL1 0x00000040 /**< RFC_OBS_MUX0 XOR bit */
661 #define RFCORE_XREG_RFC_OBS_CTRL1_RFC_OBS_MUX1 0x0000003F /**< RF Core MUX out control */
662 #define RFCORE_XREG_RFC_OBS_CTRL2_RFC_OBS_POL2 0x00000040 /**< RFC_OBS_MUX0 XOR bit */
663 #define RFCORE_XREG_RFC_OBS_CTRL2_RFC_OBS_MUX2 0x0000003F /**< RF Core MUX out control */
664 /** @} */
665 /*---------------------------------------------------------------------------*/
666 /** \name RFCORE_XREG_TXFILTCFG register bit masks
667  * @{
668  */
669 #define RFCORE_XREG_TXFILTCFG_FC 0x0000000F /**< Drives signal rfr_txfilt_fc */
670 /** @} */
671 
672 #endif /* RFCORE_XREG_H_ */
673 /** @} */