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Configuration of the Cortex-M3 Processor and Core Peripherals. More...

Interrupt Number Definition

enum  IRQn {
  NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11,
  UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2,
  SysTick_IRQn = -1, GPIO_A_IRQn = 0, GPIO_B_IRQn = 1, GPIO_C_IRQn = 2,
  GPIO_D_IRQn = 3, UART0_IRQn = 5, UART1_IRQn = 6, SSI0_IRQn = 7,
  I2C_IRQn = 8, ADC_IRQn = 14, WDT_IRQn = 18, GPT0A_IRQn = 19,
  GPT0B_IRQn = 20, GPT1A_IRQn = 21, GPT1B_IRQn = 22, GPT2A_IRQn = 23,
  GPT2B_IRQn = 24, ADC_CMP_IRQn = 25, RF_TX_RX_ALT_IRQn = 26, RF_ERR_ALT_IRQn = 27,
  SYS_CTRL_IRQn = 28, FLASH_CTRL_IRQn = 29, AES_ALT_IRQn = 30, PKA_ALT_IRQn = 31,
  SMT_ALT_IRQn = 32, MACT_ALT_IRQn = 33, SSI1_IRQn = 34, GPT3A_IRQn = 35,
  GPT3B_IRQn = 36, UDMA_SW_IRQn = 46, UDMA_ERR_IRQn = 47, USB_IRQn = 140,
  RF_TX_RX_IRQn = 141, RF_ERR_IRQn = 142, AES_IRQn = 143, PKA_IRQn = 144,
  SMT_IRQn = 145, MACT_IRQn = 146
}
 
typedef enum IRQn IRQn_Type
 

Processor and Core Peripheral Section

#define __CM3_REV   0x0200
 Core Revision r2p0.
 
#define __MPU_PRESENT   1
 MPU present or not.
 
#define __NVIC_PRIO_BITS   3
 Number of Bits used for Priority Levels.
 
#define __Vendor_SysTickConfig   0
 Set to 1 if different SysTick Config is used.
 

Detailed Description

Configuration of the Cortex-M3 Processor and Core Peripherals.

Enumeration Type Documentation

◆ IRQn

enum IRQn
Enumerator
NonMaskableInt_IRQn 

2 Non Maskable Interrupt

HardFault_IRQn 

3 HardFault Interrupt

MemoryManagement_IRQn 

4 Memory Management Interrupt

BusFault_IRQn 

5 Bus Fault Interrupt

UsageFault_IRQn 

6 Usage Fault Interrupt

SVCall_IRQn 

11 SV Call Interrupt

DebugMonitor_IRQn 

12 Debug Monitor Interrupt

PendSV_IRQn 

14 Pend SV Interrupt

SysTick_IRQn 

15 System Tick Interrupt

GPIO_A_IRQn 

GPIO port A Interrupt.

GPIO_B_IRQn 

GPIO port B Interrupt.

GPIO_C_IRQn 

GPIO port C Interrupt.

GPIO_D_IRQn 

GPIO port D Interrupt.

UART0_IRQn 

UART0 Interrupt.

UART1_IRQn 

UART1 Interrupt.

SSI0_IRQn 

SSI0 Interrupt.

I2C_IRQn 

I²C Interrupt.

ADC_IRQn 

ADC Interrupt.

WDT_IRQn 

Watchdog Timer Interrupt.

GPT0A_IRQn 

GPTimer 0A Interrupt.

GPT0B_IRQn 

GPTimer 0B Interrupt.

GPT1A_IRQn 

GPTimer 1A Interrupt.

GPT1B_IRQn 

GPTimer 1B Interrupt.

GPT2A_IRQn 

GPTimer 2A Interrupt.

GPT2B_IRQn 

GPTimer 2B Interrupt.

ADC_CMP_IRQn 

Analog Comparator Interrupt.

RF_TX_RX_ALT_IRQn 

RF Tx/Rx (Alternate) Interrupt.

RF_ERR_ALT_IRQn 

RF Error (Alternate) Interrupt.

SYS_CTRL_IRQn 

System Control Interrupt.

FLASH_CTRL_IRQn 

Flash memory Control Interrupt.

AES_ALT_IRQn 

AES (Alternate) Interrupt.

PKA_ALT_IRQn 

PKA (Alternate) Interrupt.

SMT_ALT_IRQn 

SM Timer (Alternate) Interrupt.

MACT_ALT_IRQn 

MAC Timer (Alternate) Interrupt.

SSI1_IRQn 

SSI1 Interrupt.

GPT3A_IRQn 

GPTimer 3A Interrupt.

GPT3B_IRQn 

GPTimer 3B Interrupt.

UDMA_SW_IRQn 

µDMA Software Interrupt.

UDMA_ERR_IRQn 

µDMA Error Interrupt.

USB_IRQn 

USB Interrupt.

RF_TX_RX_IRQn 

RF Tx/Rx Interrupt.

RF_ERR_IRQn 

RF Error Interrupt.

AES_IRQn 

AES Interrupt.

PKA_IRQn 

PKA Interrupt.

SMT_IRQn 

SM Timer Interrupt.

MACT_IRQn 

MAC Timer Interrupt.

Definition at line 64 of file cc2538_cm3.h.