Contiki-NG
gpio.h
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1 /*
2  * Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution.
13  *
14  * 3. Neither the name of the copyright holder nor the names of its
15  * contributors may be used to endorse or promote products derived
16  * from this software without specific prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
21  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
22  * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
23  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
27  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
29  * OF THE POSSIBILITY OF SUCH DAMAGE.
30  */
31 /**
32  * \addtogroup cc2538
33  * @{
34  *
35  * \defgroup cc2538-gpio cc2538 General-Purpose I/O
36  *
37  * Driver for the cc2538 GPIO controller
38  * @{
39  *
40  * \file
41  * Header file with register and macro declarations for the cc2538 GPIO module
42  */
43 #ifndef GPIO_H_
44 #define GPIO_H_
45 /*---------------------------------------------------------------------------*/
46 #include "contiki.h"
47 #include "dev/gpio-hal.h"
48 #include "reg.h"
49 
50 #include <stdint.h>
51 /*---------------------------------------------------------------------------*/
52 /** \name Base addresses for the GPIO register instances
53  * @{
54  */
55 #define GPIO_A_BASE 0x400D9000 /**< GPIO_A */
56 #define GPIO_B_BASE 0x400DA000 /**< GPIO_B */
57 #define GPIO_C_BASE 0x400DB000 /**< GPIO_C */
58 #define GPIO_D_BASE 0x400DC000 /**< GPIO_D */
59 /** @} */
60 /*---------------------------------------------------------------------------*/
61 /** \name Numeric representation of the four GPIO ports
62  * @{
63  */
64 #define GPIO_A_NUM 0 /**< GPIO_A: 0 */
65 #define GPIO_B_NUM 1 /**< GPIO_B: 1 */
66 #define GPIO_C_NUM 2 /**< GPIO_C: 2 */
67 #define GPIO_D_NUM 3 /**< GPIO_D: 3 */
68 /** @} */
69 /*---------------------------------------------------------------------------*/
70 /**
71  * \name GPIO Manipulation macros
72  * @{
73  */
74 /** \brief Set pins with PIN_MASK of port with PORT_BASE to input.
75  * \param PORT_BASE GPIO Port register offset
76  * \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
77  */
78 #define GPIO_SET_INPUT(PORT_BASE, PIN_MASK) \
79  do { REG((PORT_BASE) + GPIO_DIR) &= ~(PIN_MASK); } while(0)
80 
81 /** \brief Set pins with PIN_MASK of port with PORT_BASE to output.
82 * \param PORT_BASE GPIO Port register offset
83 * \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
84 */
85 #define GPIO_SET_OUTPUT(PORT_BASE, PIN_MASK) \
86  do { REG((PORT_BASE) + GPIO_DIR) |= (PIN_MASK); } while(0)
87 
88 /** \brief Return whether pins with PIN_MASK of port with PORT_BASE are set to
89  * output.
90  * \param PORT_BASE GPIO Port register offset
91  * \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
92  * \return The direction of the pins specified by PIN_MASK
93  *
94  * This macro will \e not return 0 or 1. Instead, it will return the directions
95  * of the pins specified by PIN_MASK ORed together. Thus, if 0xC3
96  * (0x80 | 0x40 | 0x02 | 0x01) is passed as the PIN_MASK and pins 7 and 0 are
97  * set to output, the macro will return 0x81.
98  */
99 #define GPIO_IS_OUTPUT(PORT_BASE, PIN_MASK) \
100  (REG((PORT_BASE) + GPIO_DIR) & (PIN_MASK))
101 
102 /** \brief Set pins with PIN_MASK of port with PORT_BASE high.
103  * \param PORT_BASE GPIO Port register offset
104  * \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
105  */
106 #define GPIO_SET_PIN(PORT_BASE, PIN_MASK) \
107  do { REG((PORT_BASE) + GPIO_DATA + ((PIN_MASK) << 2)) = 0xFF; } while(0)
108 
109 /** \brief Set pins with PIN_MASK of port with PORT_BASE low.
110 * \param PORT_BASE GPIO Port register offset
111 * \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
112 */
113 #define GPIO_CLR_PIN(PORT_BASE, PIN_MASK) \
114  do { REG((PORT_BASE) + GPIO_DATA + ((PIN_MASK) << 2)) = 0x00; } while(0)
115 
116 /** \brief Set pins with PIN_MASK of port with PORT_BASE to value.
117  * \param PORT_BASE GPIO Port register offset
118  * \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
119  * \param value The new value to write to the register. Only pins specified
120  * by PIN_MASK will be set.
121  *
122  * \note The outcome of this macro invocation will be to write to the register
123  * a new value for multiple pins. For that reason, the value argument cannot be
124  * a simple 0 or 1. Instead, it must be the value corresponding to the pins that
125  * you wish to set.
126  *
127  * Thus, if you only want to set a single pin (e.g. pin 2), do \e not pass 1,
128  * but you must pass 0x04 instead (1 << 2). This may seem counter-intuitive at
129  * first glance, but it allows a single invocation of this macro to set
130  * multiple pins in one go if so desired. For example, you can set pins 3 and 1
131  * and the same time clear pins 2 and 0. To do so, pass 0x0F as the PIN_MASK
132  * and then use 0x0A as the value ((1 << 3) | (1 << 1) for pins 3 and 1)
133  */
134 #define GPIO_WRITE_PIN(PORT_BASE, PIN_MASK, value) \
135  do { REG((PORT_BASE) + GPIO_DATA + ((PIN_MASK) << 2)) = (value); } while(0)
136 
137 /** \brief Read pins with PIN_MASK of port with PORT_BASE.
138  * \param PORT_BASE GPIO Port register offset
139  * \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
140  * \return The value of the pins specified by PIN_MASK
141  *
142  * This macro will \e not return 0 or 1. Instead, it will return the values of
143  * the pins specified by PIN_MASK ORd together. Thus, if you pass 0xC3
144  * (0x80 | 0x40 | 0x02 | 0x01) as the PIN_MASK and pins 7 and 0 are high,
145  * the macro will return 0x81.
146  */
147 #define GPIO_READ_PIN(PORT_BASE, PIN_MASK) \
148  REG((PORT_BASE) + GPIO_DATA + ((PIN_MASK) << 2))
149 
150 /** \brief Set pins with PIN_MASK of port with PORT_BASE to detect edge.
151  * \param PORT_BASE GPIO Port register offset
152  * \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
153  */
154 #define GPIO_DETECT_EDGE(PORT_BASE, PIN_MASK) \
155  do { REG((PORT_BASE) + GPIO_IS) &= ~(PIN_MASK); } while(0)
156 
157 /** \brief Set pins with PIN_MASK of port with PORT_BASE to detect level.
158  * \param PORT_BASE GPIO Port register offset
159  * \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
160  */
161 #define GPIO_DETECT_LEVEL(PORT_BASE, PIN_MASK) \
162  do { REG((PORT_BASE) + GPIO_IS) |= (PIN_MASK); } while(0)
163 
164 /** \brief Set pins with PIN_MASK of port with PORT_BASE to trigger an
165  * interrupt on both edges.
166  * \param PORT_BASE GPIO Port register offset
167  * \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
168  */
169 #define GPIO_TRIGGER_BOTH_EDGES(PORT_BASE, PIN_MASK) \
170  do { REG((PORT_BASE) + GPIO_IBE) |= (PIN_MASK); } while(0)
171 
172 /** \brief Set pins with PIN_MASK of port with PORT_BASE to trigger an
173  * interrupt on single edge (controlled by GPIO_IEV).
174  * \param PORT_BASE GPIO Port register offset
175  * \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
176  */
177 #define GPIO_TRIGGER_SINGLE_EDGE(PORT_BASE, PIN_MASK) \
178  do { REG((PORT_BASE) + GPIO_IBE) &= ~(PIN_MASK); } while(0)
179 
180 /** \brief Set pins with PIN_MASK of port with PORT_BASE to trigger an
181  * interrupt on rising edge.
182  * \param PORT_BASE GPIO Port register offset
183  * \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
184  */
185 #define GPIO_DETECT_RISING(PORT_BASE, PIN_MASK) \
186  do { REG((PORT_BASE) + GPIO_IEV) |= (PIN_MASK); } while(0)
187 
188 /** \brief Set pins with PIN_MASK of port with PORT_BASE to trigger an
189  * interrupt on falling edge.
190  * \param PORT_BASE GPIO Port register offset
191  * \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
192  */
193 #define GPIO_DETECT_FALLING(PORT_BASE, PIN_MASK) \
194  do { REG((PORT_BASE) + GPIO_IEV) &= ~(PIN_MASK); } while(0)
195 
196 /** \brief Enable interrupt triggering for pins with PIN_MASK of port with
197  * PORT_BASE.
198  * \param PORT_BASE GPIO Port register offset
199  * \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
200  */
201 #define GPIO_ENABLE_INTERRUPT(PORT_BASE, PIN_MASK) \
202  do { REG((PORT_BASE) + GPIO_IE) |= (PIN_MASK); } while(0)
203 
204 /** \brief Disable interrupt triggering for pins with PIN_MASK of port with
205  * PORT_BASE.
206  * \param PORT_BASE GPIO Port register offset
207  * \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
208  */
209 #define GPIO_DISABLE_INTERRUPT(PORT_BASE, PIN_MASK) \
210  do { REG((PORT_BASE) + GPIO_IE) &= ~(PIN_MASK); } while(0)
211 
212 /** \brief Get raw interrupt status of port with PORT_BASE.
213  * \param PORT_BASE GPIO Port register offset
214  * \return Bit-mask reflecting the raw interrupt status of all the port pins
215  *
216  * The bits set in the returned bit-mask reflect the status of the interrupts
217  * trigger conditions detected (raw, before interrupt masking), indicating that
218  * all the requirements are met, before they are finally allowed to trigger by
219  * the interrupt mask. The bits cleared indicate that corresponding input pins
220  * have not initiated an interrupt.
221  */
222 #define GPIO_GET_RAW_INT_STATUS(PORT_BASE) \
223  REG((PORT_BASE) + GPIO_RIS)
224 
225 /** \brief Get masked interrupt status of port with PORT_BASE.
226  * \param PORT_BASE GPIO Port register offset
227  * \return Bit-mask reflecting the masked interrupt status of all the port pins
228  *
229  * The bits set in the returned bit-mask reflect the status of input lines
230  * triggering an interrupt. The bits cleared indicate that either no interrupt
231  * has been generated, or the interrupt is masked. This is the state of the
232  * interrupt after interrupt masking.
233  */
234 #define GPIO_GET_MASKED_INT_STATUS(PORT_BASE) \
235  REG((PORT_BASE) + GPIO_MIS)
236 
237 /** \brief Clear interrupt triggering for pins with PIN_MASK of port with
238  * PORT_BASE.
239  * \param PORT_BASE GPIO Port register offset
240  * \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
241  */
242 #define GPIO_CLEAR_INTERRUPT(PORT_BASE, PIN_MASK) \
243  do { REG((PORT_BASE) + GPIO_IC) = (PIN_MASK); } while(0)
244 
245 /** \brief Configure the pin to be under peripheral control with PIN_MASK of
246  * port with PORT_BASE.
247  * \param PORT_BASE GPIO Port register offset
248  * \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
249  */
250 #define GPIO_PERIPHERAL_CONTROL(PORT_BASE, PIN_MASK) \
251  do { REG((PORT_BASE) + GPIO_AFSEL) |= (PIN_MASK); } while(0)
252 
253 /** \brief Configure the pin to be software controlled with PIN_MASK of port
254  * with PORT_BASE.
255  * \param PORT_BASE GPIO Port register offset
256  * \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
257  */
258 #define GPIO_SOFTWARE_CONTROL(PORT_BASE, PIN_MASK) \
259  do { REG((PORT_BASE) + GPIO_AFSEL) &= ~(PIN_MASK); } while(0)
260 
261 /** \brief Set pins with PIN_MASK of port PORT to trigger a power-up interrupt
262  * on rising edge.
263  * \param PORT GPIO Port (not port base address)
264  * \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
265  */
266 #define GPIO_POWER_UP_ON_RISING(PORT, PIN_MASK) \
267  do { REG(GPIO_PORT_TO_BASE(PORT) + GPIO_P_EDGE_CTRL) &= \
268  ~((PIN_MASK) << ((PORT) << 3)); } while(0)
269 
270 /** \brief Set pins with PIN_MASK of port PORT to trigger a power-up interrupt
271  * on falling edge.
272  * \param PORT GPIO Port (not port base address)
273  * \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
274  */
275 #define GPIO_POWER_UP_ON_FALLING(PORT, PIN_MASK) \
276  do { REG(GPIO_PORT_TO_BASE(PORT) + GPIO_P_EDGE_CTRL) |= \
277  (PIN_MASK) << ((PORT) << 3); } while(0)
278 
279 /** \brief Enable power-up interrupt triggering for pins with PIN_MASK of port
280  * PORT.
281  * \param PORT GPIO Port (not port base address)
282  * \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
283  */
284 #define GPIO_ENABLE_POWER_UP_INTERRUPT(PORT, PIN_MASK) \
285  do { REG(GPIO_PORT_TO_BASE(PORT) + GPIO_PI_IEN) |= \
286  (PIN_MASK) << ((PORT) << 3); } while(0)
287 
288 /** \brief Disable power-up interrupt triggering for pins with PIN_MASK of port
289  * PORT.
290  * \param PORT GPIO Port (not port base address)
291  * \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
292  */
293 #define GPIO_DISABLE_POWER_UP_INTERRUPT(PORT, PIN_MASK) \
294  do { REG(GPIO_PORT_TO_BASE(PORT) + GPIO_PI_IEN) &= \
295  ~((PIN_MASK) << ((PORT) << 3)); } while(0)
296 
297 /** \brief Get power-up interrupt status of port PORT.
298  * \param PORT GPIO Port (not port base address)
299  * \return Bit-mask reflecting the power-up interrupt status of all the port
300  * pins
301  */
302 #define GPIO_GET_POWER_UP_INT_STATUS(PORT) \
303  ((REG(GPIO_PORT_TO_BASE(PORT) + GPIO_IRQ_DETECT_ACK) >> ((PORT) << 3)) & 0xFF)
304 
305 /** \brief Clear power-up interrupt triggering for pins with PIN_MASK of port
306  * PORT.
307  * \param PORT GPIO Port (not port base address)
308  * \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
309  */
310 #define GPIO_CLEAR_POWER_UP_INTERRUPT(PORT, PIN_MASK) \
311  do { REG(GPIO_PORT_TO_BASE(PORT) + GPIO_IRQ_DETECT_ACK) = \
312  (PIN_MASK) << ((PORT) << 3); } while(0)
313 
314 /**
315  * \brief Converts a pin number to a pin mask
316  * \param PIN The pin number in the range [0..7]
317  * \return A pin mask which can be used as the PIN_MASK argument of the macros
318  * in this category
319  */
320 #define GPIO_PIN_MASK(PIN) (1 << (PIN))
321 
322 /**
323  * \brief Converts a port number to the port base address
324  * \param PORT The port number in the range 0 - 3. Likely GPIO_X_NUM.
325  * \return The base address for the registers corresponding to that port
326  * number.
327  */
328 #define GPIO_PORT_TO_BASE(PORT) (GPIO_A_BASE + ((PORT) << 12))
329 
330 /**
331  * \brief Converts a port/pin pair to GPIO HAL pin number
332  * \param PORT The port number in the range 0 - 3 (GPIO_n_NUM).
333  * \param PIN The pin number in the range 0 - 7.
334  * \return The pin representation using GPIO HAL semantics
335  */
336 #define GPIO_PORT_PIN_TO_GPIO_HAL_PIN(PORT, PIN) (((PORT) << 3) + (PIN))
337 /** @} */
338 /*---------------------------------------------------------------------------*/
339 /** \name GPIO Register offset declarations
340  * @{
341  */
342 #define GPIO_DATA 0x00000000 /**< Data register */
343 #define GPIO_DIR 0x00000400 /**< Data direction register */
344 #define GPIO_IS 0x00000404 /**< Interrupt sense */
345 #define GPIO_IBE 0x00000408 /**< Interrupt both edges */
346 #define GPIO_IEV 0x0000040C /**< Interrupt event */
347 #define GPIO_IE 0x00000410 /**< Interrupt mask */
348 #define GPIO_RIS 0x00000414 /**< Interrupt status - raw */
349 #define GPIO_MIS 0x00000418 /**< Interrupt status - masked */
350 #define GPIO_IC 0x0000041C /**< Interrupt clear */
351 #define GPIO_AFSEL 0x00000420 /**< Mode control select */
352 #define GPIO_GPIOLOCK 0x00000520 /**< GPIO commit unlock */
353 #define GPIO_GPIOCR 0x00000524 /**< GPIO commit */
354 #define GPIO_PMUX 0x00000700 /**< PMUX register */
355 #define GPIO_P_EDGE_CTRL 0x00000704 /**< Port edge control */
356 #define GPIO_USB_CTRL 0x00000708 /**< USB input power-up edge ctrl */
357 #define GPIO_PI_IEN 0x00000710 /**< Power-up interrupt enable */
358 #define GPIO_IRQ_DETECT_ACK 0x00000718 /**< IRQ detect ACK - I/O ports */
359 #define GPIO_USB_IRQ_ACK 0x0000071C /**< IRQ detect ACK - USB */
360 #define GPIO_IRQ_DETECT_UNMASK 0x00000720 /**< IRQ detect ACK - masked */
361 /** @} */
362 /*---------------------------------------------------------------------------*/
363 /** \name GPIO_DATA register bit masks
364  * @{
365  */
366 #define GPIO_DATA_DATA 0x000000FF /**< Input and output data */
367 /** @} */
368 /*---------------------------------------------------------------------------*/
369 /** \name GPIO_DIR register bit masks
370  * @{
371  */
372 #define GPIO_DIR_DIR 0x000000FF /**< Pin Input (0) / Output (1) */
373 /** @} */
374 /*---------------------------------------------------------------------------*/
375 /** \name GPIO_IS register bit masks
376  * @{
377  */
378 #define GPIO_IS_IS 0x000000FF /**< Detect Edge (0) / Level (1) */
379 /** @} */
380 /*---------------------------------------------------------------------------*/
381 /** \name GPIO_IBE register bit masks
382  * @{
383  */
384 #define GPIO_IBE_IBE 0x000000FF /**< Both Edges (1) / Single (0) */
385 /** @} */
386 /*---------------------------------------------------------------------------*/
387 /** \name GPIO_IEV register bit masks
388  * @{
389  */
390 #define GPIO_IEV_IEV 0x000000FF /**< Rising (1) / Falling (0) */
391 /** @} */
392 /*---------------------------------------------------------------------------*/
393 /** \name GPIO_IE register bit masks
394  * @{
395  */
396 #define GPIO_IE_IE 0x000000FF /**< Masked (0) / Not Masked (1) */
397 /** @} */
398 /*---------------------------------------------------------------------------*/
399 /** \name GPIO_RIS register bit masks
400  * @{
401  */
402 #define GPIO_RIS_RIS 0x000000FF /**< Raw interrupt status */
403 /** @} */
404 /*---------------------------------------------------------------------------*/
405 /** \name GPIO_MIS register bit masks
406  * @{
407  */
408 #define GPIO_MIS_MIS 0x000000FF /**< Masked interrupt status */
409 /** @} */
410 /*---------------------------------------------------------------------------*/
411 /** \name GPIO_IC register bit masks
412  * @{
413  */
414 #define GPIO_IC_IC 0x000000FF /**< Clear edge detection (1) */
415 /** @} */
416 /*---------------------------------------------------------------------------*/
417 /** \name GPIO_AFSEL register bit masks
418  * @{
419  */
420 #define GPIO_AFSEL_AFSEL 0x000000FF /**< Software (0) / Peripheral (1) */
421 /** @} */
422 /*---------------------------------------------------------------------------*/
423 /** \name GPIO_GPIOLOCK register bit masks
424  * @{
425  */
426 #define GPIO_GPIOLOCK_LOCK 0xFFFFFFFF /**< Locked (1) / Unlocked (0) */
427 /** @} */
428 /*---------------------------------------------------------------------------*/
429 /** \name GPIO_GPIOCR register bit masks
430  * @{
431  */
432 #define GPIO_GPIOCR_CR 0x000000FF /**< Allow alternate function (1) */
433 /** @} */
434 /*---------------------------------------------------------------------------*/
435 /** \name GPIO_PMUX register bit masks
436  * @{
437  */
438 #define GPIO_PMUX_CKOEN 0x00000080 /**< Clock out enable */
439 #define GPIO_PMUX_CKOPIN 0x00000010 /**< Decouple control pin select */
440 #define GPIO_PMUX_DCEN 0x00000008 /**< Decouple control enable */
441 #define GPIO_PMUX_DCPIN 0x00000001 /**< Decouple control pin select */
442 /** @} */
443 /*---------------------------------------------------------------------------*/
444 /** \name GPIO_P_EDGE_CTRL register bit masks.
445  * \brief Rising (0) / Falling (1)
446  * @{
447  */
448 #define GPIO_P_EDGE_CTRL_PDIRC7 0x80000000 /**< Port D bit 7 */
449 #define GPIO_P_EDGE_CTRL_PDIRC6 0x40000000 /**< Port D bit 6 */
450 #define GPIO_P_EDGE_CTRL_PDIRC5 0x20000000 /**< Port D bit 5 */
451 #define GPIO_P_EDGE_CTRL_PDIRC4 0x10000000 /**< Port D bit 4 */
452 #define GPIO_P_EDGE_CTRL_PDIRC3 0x08000000 /**< Port D bit 3 */
453 #define GPIO_P_EDGE_CTRL_PDIRC2 0x04000000 /**< Port D bit 2 */
454 #define GPIO_P_EDGE_CTRL_PDIRC1 0x02000000 /**< Port D bit 1 */
455 #define GPIO_P_EDGE_CTRL_PDIRC0 0x01000000 /**< Port D bit 0 */
456 #define GPIO_P_EDGE_CTRL_PCIRC7 0x00800000 /**< Port C bit 7 */
457 #define GPIO_P_EDGE_CTRL_PCIRC6 0x00400000 /**< Port C bit 6 */
458 #define GPIO_P_EDGE_CTRL_PCIRC5 0x00200000 /**< Port C bit 5 */
459 #define GPIO_P_EDGE_CTRL_PCIRC4 0x00100000 /**< Port C bit 4 */
460 #define GPIO_P_EDGE_CTRL_PCIRC3 0x00080000 /**< Port C bit 3 */
461 #define GPIO_P_EDGE_CTRL_PCIRC2 0x00040000 /**< Port C bit 2 */
462 #define GPIO_P_EDGE_CTRL_PCIRC1 0x00020000 /**< Port C bit 1 */
463 #define GPIO_P_EDGE_CTRL_PCIRC0 0x00010000 /**< Port C bit 0 */
464 #define GPIO_P_EDGE_CTRL_PBIRC7 0x00008000 /**< Port B bit 7 */
465 #define GPIO_P_EDGE_CTRL_PBIRC6 0x00004000 /**< Port B bit 6 */
466 #define GPIO_P_EDGE_CTRL_PBIRC5 0x00002000 /**< Port B bit 5 */
467 #define GPIO_P_EDGE_CTRL_PBIRC4 0x00001000 /**< Port B bit 4 */
468 #define GPIO_P_EDGE_CTRL_PBIRC3 0x00000800 /**< Port B bit 3 */
469 #define GPIO_P_EDGE_CTRL_PBIRC2 0x00000400 /**< Port B bit 2 */
470 #define GPIO_P_EDGE_CTRL_PBIRC1 0x00000200 /**< Port B bit 1 */
471 #define GPIO_P_EDGE_CTRL_PBIRC0 0x00000100 /**< Port B bit 0 */
472 #define GPIO_P_EDGE_CTRL_PAIRC7 0x00000080 /**< Port A bit 7 */
473 #define GPIO_P_EDGE_CTRL_PAIRC6 0x00000040 /**< Port A bit 6 */
474 #define GPIO_P_EDGE_CTRL_PAIRC5 0x00000020 /**< Port A bit 5 */
475 #define GPIO_P_EDGE_CTRL_PAIRC4 0x00000010 /**< Port A bit 4 */
476 #define GPIO_P_EDGE_CTRL_PAIRC3 0x00000008 /**< Port A bit 3 */
477 #define GPIO_P_EDGE_CTRL_PAIRC2 0x00000004 /**< Port A bit 2 */
478 #define GPIO_P_EDGE_CTRL_PAIRC1 0x00000002 /**< Port A bit 1 */
479 #define GPIO_P_EDGE_CTRL_PAIRC0 0x00000001 /**< Port A bit 0 */
480 /** @} */
481 /*---------------------------------------------------------------------------*/
482 /** \name GPIO_USB_CTRL register bit masks
483  * @{
484  */
485 #define GPIO_USB_CTRL_USB_EDGE_CTL 0x00000001 /**< Rising (0) / Falling (1) */
486 /** @} */
487 /*---------------------------------------------------------------------------*/
488 /** \name GPIO_PI_IEN register bit masks.
489  * \brief Enabled (1) / Disabled (0)
490  * @{
491  */
492 #define GPIO_PI_IEN_PDIEN7 0x80000000 /**< Port D bit 7 */
493 #define GPIO_PI_IEN_PDIEN6 0x40000000 /**< Port D bit 6 */
494 #define GPIO_PI_IEN_PDIEN5 0x20000000 /**< Port D bit 5 */
495 #define GPIO_PI_IEN_PDIEN4 0x10000000 /**< Port D bit 4 */
496 #define GPIO_PI_IEN_PDIEN3 0x08000000 /**< Port D bit 3 */
497 #define GPIO_PI_IEN_PDIEN2 0x04000000 /**< Port D bit 2 */
498 #define GPIO_PI_IEN_PDIEN1 0x02000000 /**< Port D bit 1 */
499 #define GPIO_PI_IEN_PDIEN0 0x01000000 /**< Port D bit 0 */
500 #define GPIO_PI_IEN_PCIEN7 0x00800000 /**< Port C bit 7 */
501 #define GPIO_PI_IEN_PCIEN6 0x00400000 /**< Port C bit 6 */
502 #define GPIO_PI_IEN_PCIEN5 0x00200000 /**< Port C bit 5 */
503 #define GPIO_PI_IEN_PCIEN4 0x00100000 /**< Port C bit 4 */
504 #define GPIO_PI_IEN_PCIEN3 0x00080000 /**< Port C bit 3 */
505 #define GPIO_PI_IEN_PCIEN2 0x00040000 /**< Port C bit 2 */
506 #define GPIO_PI_IEN_PCIEN1 0x00020000 /**< Port C bit 1 */
507 #define GPIO_PI_IEN_PCIEN0 0x00010000 /**< Port C bit 0 */
508 #define GPIO_PI_IEN_PBIEN7 0x00008000 /**< Port B bit 7 */
509 #define GPIO_PI_IEN_PBIEN6 0x00004000 /**< Port B bit 6 */
510 #define GPIO_PI_IEN_PBIEN5 0x00002000 /**< Port B bit 5 */
511 #define GPIO_PI_IEN_PBIEN4 0x00001000 /**< Port B bit 4 */
512 #define GPIO_PI_IEN_PBIEN3 0x00000800 /**< Port B bit 3 */
513 #define GPIO_PI_IEN_PBIEN2 0x00000400 /**< Port B bit 2 */
514 #define GPIO_PI_IEN_PBIEN1 0x00000200 /**< Port B bit 1 */
515 #define GPIO_PI_IEN_PBIEN0 0x00000100 /**< Port B bit 0 */
516 #define GPIO_PI_IEN_PAIEN7 0x00000080 /**< Port A bit 7 */
517 #define GPIO_PI_IEN_PAIEN6 0x00000040 /**< Port A bit 6 */
518 #define GPIO_PI_IEN_PAIEN5 0x00000020 /**< Port A bit 5 */
519 #define GPIO_PI_IEN_PAIEN4 0x00000010 /**< Port A bit 4 */
520 #define GPIO_PI_IEN_PAIEN3 0x00000008 /**< Port A bit 3 */
521 #define GPIO_PI_IEN_PAIEN2 0x00000004 /**< Port A bit 2 */
522 #define GPIO_PI_IEN_PAIEN1 0x00000002 /**< Port A bit 1 */
523 #define GPIO_PI_IEN_PAIEN0 0x00000001 /**< Port A bit 0 */
524 /** @} */
525 /*---------------------------------------------------------------------------*/
526 /** \name GPIO_IRQ_DETECT_ACK register bit masks
527  * \brief Detected (1) / Undetected (0)
528  * @{
529  */
530 #define GPIO_IRQ_DETECT_ACK_PDIACK7 0x80000000 /**< Port D bit 7 */
531 #define GPIO_IRQ_DETECT_ACK_PDIACK6 0x40000000 /**< Port D bit 6 */
532 #define GPIO_IRQ_DETECT_ACK_PDIACK5 0x20000000 /**< Port D bit 5 */
533 #define GPIO_IRQ_DETECT_ACK_PDIACK4 0x10000000 /**< Port D bit 4 */
534 #define GPIO_IRQ_DETECT_ACK_PDIACK3 0x08000000 /**< Port D bit 3 */
535 #define GPIO_IRQ_DETECT_ACK_PDIACK2 0x04000000 /**< Port D bit 2 */
536 #define GPIO_IRQ_DETECT_ACK_PDIACK1 0x02000000 /**< Port D bit 1 */
537 #define GPIO_IRQ_DETECT_ACK_PDIACK0 0x01000000 /**< Port D bit 0 */
538 #define GPIO_IRQ_DETECT_ACK_PCIACK7 0x00800000 /**< Port C bit 7 */
539 #define GPIO_IRQ_DETECT_ACK_PCIACK6 0x00400000 /**< Port C bit 6 */
540 #define GPIO_IRQ_DETECT_ACK_PCIACK5 0x00200000 /**< Port C bit 5 */
541 #define GPIO_IRQ_DETECT_ACK_PCIACK4 0x00100000 /**< Port C bit 4 */
542 #define GPIO_IRQ_DETECT_ACK_PCIACK3 0x00080000 /**< Port C bit 3 */
543 #define GPIO_IRQ_DETECT_ACK_PCIACK2 0x00040000 /**< Port C bit 2 */
544 #define GPIO_IRQ_DETECT_ACK_PCIACK1 0x00020000 /**< Port C bit 1 */
545 #define GPIO_IRQ_DETECT_ACK_PCIACK0 0x00010000 /**< Port C bit 0 */
546 #define GPIO_IRQ_DETECT_ACK_PBIACK7 0x00008000 /**< Port B bit 7 */
547 #define GPIO_IRQ_DETECT_ACK_PBIACK6 0x00004000 /**< Port B bit 6 */
548 #define GPIO_IRQ_DETECT_ACK_PBIACK5 0x00002000 /**< Port B bit 5 */
549 #define GPIO_IRQ_DETECT_ACK_PBIACK4 0x00001000 /**< Port B bit 4 */
550 #define GPIO_IRQ_DETECT_ACK_PBIACK3 0x00000800 /**< Port B bit 3 */
551 #define GPIO_IRQ_DETECT_ACK_PBIACK2 0x00000400 /**< Port B bit 2 */
552 #define GPIO_IRQ_DETECT_ACK_PBIACK1 0x00000200 /**< Port B bit 1 */
553 #define GPIO_IRQ_DETECT_ACK_PBIACK0 0x00000100 /**< Port B bit 0 */
554 #define GPIO_IRQ_DETECT_ACK_PAIACK7 0x00000080 /**< Port A bit 7 */
555 #define GPIO_IRQ_DETECT_ACK_PAIACK6 0x00000040 /**< Port A bit 6 */
556 #define GPIO_IRQ_DETECT_ACK_PAIACK5 0x00000020 /**< Port A bit 5 */
557 #define GPIO_IRQ_DETECT_ACK_PAIACK4 0x00000010 /**< Port A bit 4 */
558 #define GPIO_IRQ_DETECT_ACK_PAIACK3 0x00000008 /**< Port A bit 3 */
559 #define GPIO_IRQ_DETECT_ACK_PAIACK2 0x00000004 /**< Port A bit 2 */
560 #define GPIO_IRQ_DETECT_ACK_PAIACK1 0x00000002 /**< Port A bit 1 */
561 #define GPIO_IRQ_DETECT_ACK_PAIACK0 0x00000001 /**< Port A bit 0 */
562 /** @} */
563 /*---------------------------------------------------------------------------*/
564 /** \name GPIO_USB_IRQ_ACK register bit masks
565  * @{
566  */
567 #define GPIO_USB_IRQ_ACK_USBACK 0x00000001 /**< Detected (1) / Not detected (0) */
568 /** @} */
569 /*---------------------------------------------------------------------------*/
570 /** \name GPIO_IRQ_DETECT_UNMASK register bit masks.
571  * \brief Detected (1) / Not detected (0)
572  * @{
573  */
574 #define GPIO_IRQ_DETECT_UNMASK_PDIACK7 0x80000000 /**< Port D bit 7 */
575 #define GPIO_IRQ_DETECT_UNMASK_PDIACK6 0x40000000 /**< Port D bit 6 */
576 #define GPIO_IRQ_DETECT_UNMASK_PDIACK5 0x20000000 /**< Port D bit 5 */
577 #define GPIO_IRQ_DETECT_UNMASK_PDIACK4 0x10000000 /**< Port D bit 4 */
578 #define GPIO_IRQ_DETECT_UNMASK_PDIACK3 0x08000000 /**< Port D bit 3 */
579 #define GPIO_IRQ_DETECT_UNMASK_PDIACK2 0x04000000 /**< Port D bit 2 */
580 #define GPIO_IRQ_DETECT_UNMASK_PDIACK1 0x02000000 /**< Port D bit 1 */
581 #define GPIO_IRQ_DETECT_UNMASK_PDIACK0 0x01000000 /**< Port D bit 0 */
582 #define GPIO_IRQ_DETECT_UNMASK_PCIACK7 0x00800000 /**< Port C bit 7 */
583 #define GPIO_IRQ_DETECT_UNMASK_PCIACK6 0x00400000 /**< Port C bit 6 */
584 #define GPIO_IRQ_DETECT_UNMASK_PCIACK5 0x00200000 /**< Port C bit 5 */
585 #define GPIO_IRQ_DETECT_UNMASK_PCIACK4 0x00100000 /**< Port C bit 4 */
586 #define GPIO_IRQ_DETECT_UNMASK_PCIACK3 0x00080000 /**< Port C bit 3 */
587 #define GPIO_IRQ_DETECT_UNMASK_PCIACK2 0x00040000 /**< Port C bit 2 */
588 #define GPIO_IRQ_DETECT_UNMASK_PCIACK1 0x00020000 /**< Port C bit 1 */
589 #define GPIO_IRQ_DETECT_UNMASK_PCIACK0 0x00010000 /**< Port C bit 0 */
590 #define GPIO_IRQ_DETECT_UNMASK_PBIACK7 0x00008000 /**< Port B bit 7 */
591 #define GPIO_IRQ_DETECT_UNMASK_PBIACK6 0x00004000 /**< Port B bit 6 */
592 #define GPIO_IRQ_DETECT_UNMASK_PBIACK5 0x00002000 /**< Port B bit 5 */
593 #define GPIO_IRQ_DETECT_UNMASK_PBIACK4 0x00001000 /**< Port B bit 4 */
594 #define GPIO_IRQ_DETECT_UNMASK_PBIACK3 0x00000800 /**< Port B bit 3 */
595 #define GPIO_IRQ_DETECT_UNMASK_PBIACK2 0x00000400 /**< Port B bit 2 */
596 #define GPIO_IRQ_DETECT_UNMASK_PBIACK1 0x00000200 /**< Port B bit 1 */
597 #define GPIO_IRQ_DETECT_UNMASK_PBIACK0 0x00000100 /**< Port B bit 0 */
598 #define GPIO_IRQ_DETECT_UNMASK_PAIACK7 0x00000080 /**< Port A bit 7 */
599 #define GPIO_IRQ_DETECT_UNMASK_PAIACK6 0x00000040 /**< Port A bit 6 */
600 #define GPIO_IRQ_DETECT_UNMASK_PAIACK5 0x00000020 /**< Port A bit 5 */
601 #define GPIO_IRQ_DETECT_UNMASK_PAIACK4 0x00000010 /**< Port A bit 4 */
602 #define GPIO_IRQ_DETECT_UNMASK_PAIACK3 0x00000008 /**< Port A bit 3 */
603 #define GPIO_IRQ_DETECT_UNMASK_PAIACK2 0x00000004 /**< Port A bit 2 */
604 #define GPIO_IRQ_DETECT_UNMASK_PAIACK1 0x00000002 /**< Port A bit 1 */
605 #define GPIO_IRQ_DETECT_UNMASK_PAIACK0 0x00000001 /**< Port A bit 0 */
606 /** @} */
607 /*---------------------------------------------------------------------------*/
608 #endif /* GPIO_H_ */
609 
610 /**
611  * @}
612  * @}
613  */
Header file with register manipulation macro definitions.
Header file for the GPIO HAL.