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at86rf215-registermap.h
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1/*
2 * Copyright (c) 2023, ComLab, Jozef Stefan Institute - https://e6.ijs.si/
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the copyright holder nor the names of its
14 * contributors may be used to endorse or promote products derived
15 * from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
20 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
21 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
26 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
28 * OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30/*---------------------------------------------------------------------------*/
31/**
32 * \file
33 * Registermap for the AT86RF215
34 *
35 * Note that currently only registers for RF24 and BBC1 are defined.
36 *
37 * \author
38 * Grega Morano <grega.morano@ijs.si>
39*/
40
41#ifndef AT86RF215_REGISTERMAP_H_
42#define AT86RF215_REGISTERMAP_H_
43
44/* Defines for SPI */
45#define SPI_CMD_READ (0x00)
46#define SPI_CMD_WRITE (0x80)
47
48/* Registermap */
49enum {
50 RG_RF09_IRQS = (0x0000),
51 RG_RF24_IRQS = (0x0001),
52 RG_BBC0_IRQS = (0x0002),
53 RG_BBC1_IRQS = (0x0003),
54 RG_RF_RST = (0x0005),
55 RG_RF_CFG = (0x0006),
56 RG_RF_CLKO = (0x0007),
57 RG_RF_BMDVC = (0x0008),
58 RG_RF_XOC = (0x0009),
59 RG_RF_IQIFC0 = (0x000A),
60 RG_RF_IQIFC1 = (0x000B),
61 RG_RF_IQIFC2 = (0x000C),
62 RG_RF_PN = (0x000D),
63 RG_RF_VN = (0x000E),
64 RG_RF09_IRQM = (0x0100),
65 RG_RF09_AUXS = (0x0101),
66 RG_RF09_STATE = (0x0102),
67 RG_RF09_CMD = (0x0103),
68 RG_RF09_CS = (0x0104),
69 RG_RF09_CCF0L = (0x0105),
70 RG_RF09_CCF0H = (0x0106),
71 RG_RF09_CNL = (0x0107),
72 RG_RF09_CNM = (0x0108),
73 RG_RF09_RXBWC = (0x0109),
74 RG_RF09_RXDFE = (0x010A),
75 RG_RF09_AGCC = (0x010B),
76 RG_RF09_AGCS = (0x010C),
77 RG_RF09_RSSI = (0x010D),
78 RG_RF09_EDC = (0x010E),
79 RG_RF09_EDD = (0x010F),
80 RG_RF09_EDV = (0x0110),
81 RG_RF09_RNDV = (0x0111),
82 RG_RF09_TXCUTC = (0x0112),
83 RG_RF09_TXDFE = (0x0113),
84 RG_RF09_PAC = (0x0114),
85 RG_RF09_PADFE = (0x0116),
86 RG_RF09_PLL = (0x0121),
87 RG_RF09_PLLCF = (0x0122),
88 RG_RF09_TXCI = (0x0125),
89 RG_RF09_TXCQ = (0x0126),
90 RG_RF09_TXDACI = (0x0127),
91 RG_RF09_TXDACQ = (0x0128),
92 RG_RF24_IRQM = (0x0200),
93 RG_RF24_AUXS = (0x0201),
94 RG_RF24_STATE = (0x0202),
95 RG_RF24_CMD = (0x0203),
96 RG_RF24_CS = (0x0204),
97 RG_RF24_CCF0L = (0x0205),
98 RG_RF24_CCF0H = (0x0206),
99 RG_RF24_CNL = (0x0207),
100 RG_RF24_CNM = (0x0208),
101 RG_RF24_RXBWC = (0x0209),
102 RG_RF24_RXDFE = (0x020A),
103 RG_RF24_AGCC = (0x020B),
104 RG_RF24_AGCS = (0x020C),
105 RG_RF24_RSSI = (0x020D),
106 RG_RF24_EDC = (0x020E),
107 RG_RF24_EDD = (0x020F),
108 RG_RF24_EDV = (0x0210),
109 RG_RF24_RNDV = (0x0211),
110 RG_RF24_TXCUTC = (0x0212),
111 RG_RF24_TXDFE = (0x0213),
112 RG_RF24_PAC = (0x0214),
113 RG_RF24_PADFE = (0x0216),
114 RG_RF24_PLL = (0x0221),
115 RG_RF24_PLLCF = (0x0222),
116 RG_RF24_TXCI = (0x0225),
117 RG_RF24_TXCQ = (0x0226),
118 RG_RF24_TXDACI = (0x0227),
119 RG_RF24_TXDACQ = (0x0228),
120 RG_BBC0_IRQM = (0x0300),
121 RG_BBC0_PC = (0x0301),
122 RG_BBC0_PS = (0x0302),
123 RG_BBC0_RXFLL = (0x0304),
124 RG_BBC0_RXFLH = (0x0305),
125 RG_BBC0_TXFLL = (0x0306),
126 RG_BBC0_TXFLH = (0x0307),
127 RG_BBC0_FBLL = (0x0308),
128 RG_BBC0_FBLH = (0x0309),
129 RG_BBC0_FBLIL = (0x030A),
130 RG_BBC0_FBLIH = (0x030B),
131 RG_BBC0_OFDMPHRTX = (0x030C),
132 RG_BBC0_OFDMPHRRX = (0x030D),
133 RG_BBC0_OFDMC = (0x030E),
134 RG_BBC0_OFDMSW = (0x030F),
135 RG_BBC0_OQPSKC0 = (0x0310),
136 RG_BBC0_OQPSKC1 = (0x0311),
137 RG_BBC0_OQPSKC2 = (0x0312),
138 RG_BBC0_OQPSKC3 = (0x0313),
139 RG_BBC0_OQPSKPHRTX = (0x0314),
140 RG_BBC0_OQPSKPHRRX = (0x0315),
141 RG_BBC0_AFC0 = (0x0320),
142 RG_BBC0_AFC1 = (0x0321),
143 RG_BBC0_AFFTM = (0x0322),
144 RG_BBC0_AFFVM = (0x0323),
145 RG_BBC0_AFS = (0x0324),
146 RG_BBC0_MACEA0 = (0x0325),
147 RG_BBC0_MACEA1 = (0x0326),
148 RG_BBC0_MACEA2 = (0x0327),
149 RG_BBC0_MACEA3 = (0x0328),
150 RG_BBC0_MACEA4 = (0x0329),
151 RG_BBC0_MACEA5 = (0x032A),
152 RG_BBC0_MACEA6 = (0x032B),
153 RG_BBC0_MACEA7 = (0x032C),
154 RG_BBC0_MACPID0F0 = (0x032D),
155 RG_BBC0_MACPID1F0 = (0x032E),
156 RG_BBC0_MACSHA0F0 = (0x032F),
157 RG_BBC0_MACSHA1F0 = (0x0330),
158 RG_BBC0_MACPID0F1 = (0x0331),
159 RG_BBC0_MACPID1F1 = (0x0332),
160 RG_BBC0_MACSHA0F1 = (0x0333),
161 RG_BBC0_MACSHA1F1 = (0x0334),
162 RG_BBC0_MACPID0F2 = (0x0335),
163 RG_BBC0_MACPID1F2 = (0x0336),
164 RG_BBC0_MACSHA0F2 = (0x0337),
165 RG_BBC0_MACSHA1F2 = (0x0338),
166 RG_BBC0_MACPID0F3 = (0x0339),
167 RG_BBC0_MACPID1F3 = (0x033A),
168 RG_BBC0_MACSHA0F3 = (0x033B),
169 RG_BBC0_MACSHA1F3 = (0x033C),
170 RG_BBC0_AMCS = (0x0340),
171 RG_BBC0_AMEDT = (0x0341),
172 RG_BBC0_AMAACKPD = (0x0342),
173 RG_BBC0_AMAACKTL = (0x0343),
174 RG_BBC0_AMAACKTH = (0x0344),
175 RG_BBC0_FSKC0 = (0x0360),
176 RG_BBC0_FSKC1 = (0x0361),
177 RG_BBC0_FSKC2 = (0x0362),
178 RG_BBC0_FSKC3 = (0x0363),
179 RG_BBC0_FSKC4 = (0x0364),
180 RG_BBC0_FSKPLL = (0x0365),
181 RG_BBC0_FSKSFD0L = (0x0366),
182 RG_BBC0_FSKSFD0H = (0x0367),
183 RG_BBC0_FSKSFD1L = (0x0368),
184 RG_BBC0_FSKSFD1H = (0x0369),
185 RG_BBC0_FSKPHRTX = (0x036A),
186 RG_BBC0_FSKPHRRX = (0x036B),
187 RG_BBC0_FSKRPC = (0x036C),
188 RG_BBC0_FSKRPCONT = (0x036D),
189 RG_BBC0_FSKRPCOFFT = (0x036E),
190 RG_BBC0_FSKRRXFLL = (0x0370),
191 RG_BBC0_FSKRRXFLH = (0x0371),
192 RG_BBC0_FSKDM = (0x0372),
193 RG_BBC0_FSKPE0 = (0x0373),
194 RG_BBC0_FSKPE1 = (0x0374),
195 RG_BBC0_FSKPE2 = (0x0375),
196 RG_BBC0_PMUC = (0x0380),
197 RG_BBC0_PMUVAL = (0x0381),
198 RG_BBC0_PMUQF = (0x0382),
199 RG_BBC0_PMUI = (0x0383),
200 RG_BBC0_PMUQ = (0x0384),
201 RG_BBC0_CNTC = (0x0390),
202 RG_BBC0_CNT0 = (0x0391),
203 RG_BBC0_CNT1 = (0x0392),
204 RG_BBC0_CNT2 = (0x0393),
205 RG_BBC0_CNT3 = (0x0394),
206 RG_BBC1_IRQM = (0x0400),
207 RG_BBC1_PC = (0x0401),
208 RG_BBC1_PS = (0x0402),
209 RG_BBC1_RXFLL = (0x0404),
210 RG_BBC1_RXFLH = (0x0405),
211 RG_BBC1_TXFLL = (0x0406),
212 RG_BBC1_TXFLH = (0x0407),
213 RG_BBC1_FBLL = (0x0408),
214 RG_BBC1_FBLH = (0x0409),
215 RG_BBC1_FBLIL = (0x040A),
216 RG_BBC1_FBLIH = (0x040B),
217 RG_BBC1_OFDMPHRTX = (0x040C),
218 RG_BBC1_OFDMPHRRX = (0x040D),
219 RG_BBC1_OFDMC = (0x040E),
220 RG_BBC1_OFDMSW = (0x040F),
221 RG_BBC1_OQPSKC0 = (0x0410),
222 RG_BBC1_OQPSKC1 = (0x0411),
223 RG_BBC1_OQPSKC2 = (0x0412),
224 RG_BBC1_OQPSKC3 = (0x0413),
225 RG_BBC1_OQPSKPHRTX = (0x0414),
226 RG_BBC1_OQPSKPHRRX = (0x0415),
227 RG_BBC1_AFC0 = (0x0420),
228 RG_BBC1_AFC1 = (0x0421),
229 RG_BBC1_AFFTM = (0x0422),
230 RG_BBC1_AFFVM = (0x0423),
231 RG_BBC1_AFS = (0x0424),
232 RG_BBC1_MACEA0 = (0x0425),
233 RG_BBC1_MACEA1 = (0x0426),
234 RG_BBC1_MACEA2 = (0x0427),
235 RG_BBC1_MACEA3 = (0x0428),
236 RG_BBC1_MACEA4 = (0x0429),
237 RG_BBC1_MACEA5 = (0x042A),
238 RG_BBC1_MACEA6 = (0x042B),
239 RG_BBC1_MACEA7 = (0x042C),
240 RG_BBC1_MACPID0F0 = (0x042D),
241 RG_BBC1_MACPID1F0 = (0x042E),
242 RG_BBC1_MACSHA0F0 = (0x042F),
243 RG_BBC1_MACSHA1F0 = (0x0430),
244 RG_BBC1_MACPID0F1 = (0x0431),
245 RG_BBC1_MACPID1F1 = (0x0432),
246 RG_BBC1_MACSHA0F1 = (0x0433),
247 RG_BBC1_MACSHA1F1 = (0x0434),
248 RG_BBC1_MACPID0F2 = (0x0435),
249 RG_BBC1_MACPID1F2 = (0x0436),
250 RG_BBC1_MACSHA0F2 = (0x0437),
251 RG_BBC1_MACSHA1F2 = (0x0438),
252 RG_BBC1_MACPID0F3 = (0x0439),
253 RG_BBC1_MACPID1F3 = (0x043A),
254 RG_BBC1_MACSHA0F3 = (0x043B),
255 RG_BBC1_MACSHA1F3 = (0x043C),
256 RG_BBC1_AMCS = (0x0440),
257 RG_BBC1_AMEDT = (0x0441),
258 RG_BBC1_AMAACKPD = (0x0442),
259 RG_BBC1_AMAACKTL = (0x0443),
260 RG_BBC1_AMAACKTH = (0x0444),
261 RG_BBC1_FSKC0 = (0x0460),
262 RG_BBC1_FSKC1 = (0x0461),
263 RG_BBC1_FSKC2 = (0x0462),
264 RG_BBC1_FSKC3 = (0x0463),
265 RG_BBC1_FSKC4 = (0x0464),
266 RG_BBC1_FSKPLL = (0x0465),
267 RG_BBC1_FSKSFD0L = (0x0466),
268 RG_BBC1_FSKSFD0H = (0x0467),
269 RG_BBC1_FSKSFD1L = (0x0468),
270 RG_BBC1_FSKSFD1H = (0x0469),
271 RG_BBC1_FSKPHRTX = (0x046A),
272 RG_BBC1_FSKPHRRX = (0x046B),
273 RG_BBC1_FSKRPC = (0x046C),
274 RG_BBC1_FSKRPCONT = (0x046D),
275 RG_BBC1_FSKRPCOFFT = (0x046E),
276 RG_BBC1_FSKRRXFLL = (0x0470),
277 RG_BBC1_FSKRRXFLH = (0x0471),
278 RG_BBC1_FSKDM = (0x0472),
279 RG_BBC1_FSKPE0 = (0x0473),
280 RG_BBC1_FSKPE1 = (0x0474),
281 RG_BBC1_FSKPE2 = (0x0475),
282 RG_BBC1_PMUC = (0x0480),
283 RG_BBC1_PMUVAL = (0x0481),
284 RG_BBC1_PMUQF = (0x0482),
285 RG_BBC1_PMUI = (0x0483),
286 RG_BBC1_PMUQ = (0x0484),
287 RG_BBC1_CNTC = (0x0490),
288 RG_BBC1_CNT0 = (0x0491),
289 RG_BBC1_CNT1 = (0x0492),
290 RG_BBC1_CNT2 = (0x0493),
291 RG_BBC1_CNT3 = (0x0494),
292
293 RG_BBC0_FBRXS = (0x2000),
294 RG_BBC0_FBRXE = (0x27FE),
295 RG_BBC0_FBTXS = (0x2800),
296 RG_BBC0_FBTXE = (0x2FFE),
297 RG_BBC1_FBRXS = (0x3000),
298 RG_BBC1_FBRXE = (0x37FE),
299 RG_BBC1_FBTXS = (0x3800),
300 RG_BBC1_FBTXE = (0x3FFE),
301};
302
303/*---------------------------------------------------------*/
304
305/*---------------------------------------------------------*/
306//#define RG_RF_RST (0x0005)
307
308//#define RG_RF_IQIFC1 (0x000B)
309#define SR_SKEWDRV RG_RF_IQIFC1, 0x03, 0
310#define SR_CHPM RG_RF_IQIFC1, 0x70, 4
311#define SR_FAILSF RG_RF_IQIFC1, 0x80, 7
312
313
314/*---------------------------------------------------------*/
315/* State machine */
316/*---------------------------------------------------------*/
317//#define RG_RF24_STATE (0x0202)
318#define SR_RF24_STATE RG_RF24_STATE, 0x07, 0
319enum {
320 RF_STATE_TRXOFF = 0x2,
321 RF_STATE_TXPREP = 0x3,
322 RF_STATE_TX = 0x4,
323 RF_STATE_RX = 0x5,
324 RF_STATE_TRANSITION = 0x6,
325 RF_STATE_RESET = 0x7
326};
327
328//#define RG_RF24_CMD (0x0203)
329#define SR_RF24_CMD RG_RF24_CMD, 0x07, 0
330enum {
331 RF_CMD_NOP = 0x0,
332 RF_CMD_SLEEP = 0x1,
333 RF_CMD_TRXOFF = 0x2,
334 RF_CMD_TXPREP = 0x3,
335 RF_CMD_TX = 0x4,
336 RF_CMD_RX = 0x5,
337 RF_CMD_RESET = 0x7
338};
339
340
341/*---------------------------------------------------------*/
342/* IRQ registers */
343/*---------------------------------------------------------*/
344//#define RG_RF_CFG (0x0006)
345#define SR_DRV RG_RF_CFG, 0x03, 0
346#define SR_IRQP RG_RF_CFG, 0x04, 2
347#define SR_IRQMM RG_RF_CFG, 0x08, 3
348
349//#define RG_RF24_IRQM (0x0200)
350#define SR_RF24_IRQ_MASK RG_RF24_IRQM, 0x3F, 0
351enum {
352 IRQ1_WAKEUP = 1 << 0,
353 IRQ2_TRXRDY = 1 << 1,
354 IRQ3_EDC = 1 << 2,
355 IRQ4_BATLOW = 1 << 3,
356 IRQ5_TRXERR = 1 << 4,
357 IRQ6_IQIFSF = 1 << 5,
358};
359//#define RG_RF24_IRQS (0x0001)
360#define SR_RF24_IRQ_STATUS RG_RF24_IRQS, 0x3F, 0
361
362//#define RG_BBC1_IRQM (0x0400)
363#define SR_BBC1_IRQ_MASK RG_BBC1_IRQM, 0xFF, 0
364enum {
365 IRQ1_RXFS = 1 << 0,
366 IRQ2_RXFE = 1 << 1,
367 IRQ3_RXAM = 1 << 2,
368 IRQ4_RXEM = 1 << 3,
369 IRQ5_TXFE = 1 << 4,
370 IRQ6_AGCH = 1 << 5,
371 IRQ7_AGCR = 1 << 6,
372 IRQ8_FBLI = 1 << 7
373};
374
375//#dfine RG_BBC1_IRQS (0x0003)
376#define SR_BBC1_IRQ_STATUS RG_BBC1_IRQS, 0xFF, 0
377
378
379/*---------------------------------------------------------*/
380/* Output power config */
381/*---------------------------------------------------------*/
382//#define RG_RF24_PAC (0x0214)
383#define SR_RF24_TXPWR RG_RF24_PAC, 0x1F, 0
384#define SR_RF24_PACUR RG_RF24_PAC, 0x60, 5
385
386//#define RG_RF24_RSSI
387#define SR_RF24_RSSI RG_RF24_RSSI, 0xFF, 0
388
389/*---------------------------------------------------------*/
390/* Frequency registers */
391/*---------------------------------------------------------*/
392//#define RG_RF24_CS
393#define SR_RF24_CS RG_RF24_CS, 0xFF, 0
394
395//#define RG_RF24_CCF0L
396#define SR_RF24_CCF0L RG_RF24_CCF0L, 0xFF, 0
397
398//#define RG_RF24_CCF0H
399#define SR_RF24_CCF0H RG_RF24_CCF0H, 0xFF, 0
400
401//#define RG_RF24_CNL
402#define SR_RF24_CNL RG_RF24_CNL, 0xFF, 0
403
404//#define RG_RF24_CNM
405#define SR_RF24_CHN RG_RF24_CNM, 0x01, 0
406#define SR_RF24_CM RG_RF24_CNM, 0xC0, 6
407
408enum {
409 CHANNEL_MODE_IEEE_COMPLIANT = 0x0,
410 //
411 CHANNEL_MODE_09_FINE_RESOLUTION = 0x2,
412 CHANNEL_MODE_24_FINE_RESOLUTION = 0x3,
413};
414
415
416/*---------------------------------------------------------*/
417/* PHY control (PC) */
418/*---------------------------------------------------------*/
419//#define RG_BBC1_PC (0x0401)
420#define SR_BBC1_CTX RG_BBC1_PC, 0x80, 7
421#define SR_BBC1_FCSFE RG_BBC1_PC, 0x40, 6
422#define SR_BBC1_FCSOK RG_BBC1_PC, 0x20, 5
423#define SR_BBC1_TXAFCS RG_BBC1_PC, 0x10, 4
424#define SR_BBC1_FCST RG_BBC1_PC, 0x08, 3
425#define SR_BBC1_BBEN RG_BBC1_PC, 0x04, 2
426#define SR_BBC1_PT RG_BBC1_PC, 0x03, 0
427
428enum {
429 PHY_TYPE_BB_PHYOFF = 0x0,
430 PHY_TYPE_BB_MRFSK = 0x1,
431 PHY_TYPE_BB_MROFDM = 0x2,
432 PHY_TYPE_BB_MROQPSK = 0x3
433};
434
435
436/*---------------------------------------------------------*/
437/* Auto modes (AACK, CCATX and TX2RX) */
438/*---------------------------------------------------------*/
439//#define RG_BBC1_AMCS (0x0)
440#define SR_BBC1_AACKFT RG_BBC1_AMCS, 0x80, 7
441#define SR_BBC1_AACKFA RG_BBC1_AMCS, 0x40, 6
442#define SR_BBC1_AACKDR RG_BBC1_AMCS, 0x20, 5
443#define SR_BBC1_AACKS RG_BBC1_AMCS, 0x10, 4
444#define SR_BBC1_AACK RG_BBC1_AMCS, 0x80, 3
445#define SR_BBC1_CCAED RG_BBC1_AMCS, 0x04, 2
446#define SR_BBC1_CCATX RG_BBC1_AMCS, 0x02, 1
447#define SR_BBC1_TX2RX RG_BBC1_AMCS, 0x01, 0
448
449
450/*---------------------------------------------------------*/
451/* Phase Measurement Unit */
452/*---------------------------------------------------------*/
453//#define RG_BBC1_PMUC (0x0480)
454#define SR_BBC1_PMU_EN RG_BBC1_PMUC, 0x01, 0
455#define SR_BBC1_PMU_AVG RG_BBC1_PMUC, 0x02, 1
456#define SR_BBC1_PMU_SYNC RG_BBC1_PMUC, 0x1C, 2
457#define SR_BBC1_PMU_FED RG_BBC1_PMUC, 0x20, 5
458#define SR_BBC1_PMU_IQSEL RG_BBC1_PMUC, 0x40, 6
459#define SR_BBC1_PMU_CCFTS RG_BBC1_PMUC, 0x80, 7
460
461#endif /* AT86RF215_REGISTERMAP_H_ */