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uart.h
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1/*
2 * Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * 3. Neither the name of the copyright holder nor the names of its
15 * contributors may be used to endorse or promote products derived
16 * from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
21 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
22 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
29 * OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31/**
32 * \addtogroup cc2538
33 * @{
34 *
35 * \defgroup cc2538-uart cc2538 UART
36 *
37 * Driver for the cc2538 UART controller
38 * @{
39 *
40 * \file
41 * Header file for the cc2538 UART driver
42 */
43#ifndef UART_H_
44#define UART_H_
45
46#include "contiki.h"
47
48#include <stdint.h>
49/*---------------------------------------------------------------------------*/
50/** \name UART instance count
51 * @{
52 */
53#define UART_INSTANCE_COUNT 2
54/** @} */
55/*---------------------------------------------------------------------------*/
56/** \name UART base addresses
57 * @{
58 */
59#define UART_0_BASE 0x4000C000
60#define UART_1_BASE 0x4000D000
61/** @} */
62/*---------------------------------------------------------------------------*/
63/** \name UART Register Offsets
64 * @{
65 */
66#define UART_DR 0x00000000 /**< UART data */
67#define UART_RSR 0x00000004 /**< UART RX status and err clear */
68#define UART_ECR 0x00000004 /**< UART RX status and err clear */
69#define UART_FR 0x00000018 /**< UART flag */
70#define UART_ILPR 0x00000020 /**< UART IrDA low-power */
71#define UART_IBRD 0x00000024 /**< UART BAUD divisor: integer */
72#define UART_FBRD 0x00000028 /**< UART BAUD divisor: fractional */
73#define UART_LCRH 0x0000002C /**< UART line control */
74#define UART_CTL 0x00000030 /**< UART control */
75#define UART_IFLS 0x00000034 /**< UART interrupt FIFO level */
76#define UART_IM 0x00000038 /**< UART interrupt mask */
77#define UART_RIS 0x0000003C /**< UART raw interrupt status */
78#define UART_MIS 0x00000040 /**< UART masked interrupt status */
79#define UART_ICR 0x00000044 /**< UART interrupt clear */
80#define UART_DMACTL 0x00000048 /**< UART DMA control */
81#define UART_LCTL 0x00000090 /**< UART LIN control */
82#define UART_LSS 0x00000094 /**< UART LIN snap shot */
83#define UART_LTIM 0x00000098 /**< UART LIN timer */
84#define UART_NINEBITADDR 0x000000A4 /**< UART 9-bit self address */
85#define UART_NINEBITAMASK 0x000000A8 /**< UART 9-bit self address mask */
86#define UART_PP 0x00000FC0 /**< UART peripheral properties */
87#define UART_CC 0x00000FC8 /**< UART clock configuration */
88/** @} */
89/*---------------------------------------------------------------------------*/
90/** \name UART_DR Register Bit-Masks
91 * @{
92 */
93#define UART_DR_OE 0x00000800 /**< UART overrun error */
94#define UART_DR_BE 0x00000400 /**< UART break error */
95#define UART_DR_PE 0x00000200 /**< UART parity error */
96#define UART_DR_FE 0x00000100 /**< UART framing error */
97#define UART_DR_DATA 0x000000FF /**< Data transmitted or received */
98/** @} */
99/*---------------------------------------------------------------------------*/
100/** \name UART_RSR Register Bit-Masks
101 * @{
102 */
103#define UART_RSR_OE 0x00000008 /**< UART overrun error */
104#define UART_RSR_BE 0x00000004 /**< UART break error */
105#define UART_RSR_PE 0x00000002 /**< UART parity error */
106#define UART_RSR_FE 0x00000001 /**< UART framing error */
107/** @} */
108/*---------------------------------------------------------------------------*/
109/** \name UART_ECR Register Bit-Masks
110 * @{
111 */
112#define UART_ECR_DATA 0x000000FF /**< Error clear */
113/** @} */
114/*---------------------------------------------------------------------------*/
115/** \name UART_FR Register Bit-Masks
116 * @{
117 */
118#define UART_FR_TXFE 0x00000080 /**< UART transmit FIFO empty */
119#define UART_FR_RXFF 0x00000040 /**< UART receive FIFO full */
120#define UART_FR_TXFF 0x00000020 /**< UART transmit FIFO full */
121#define UART_FR_RXFE 0x00000010 /**< UART receive FIFO empty */
122#define UART_FR_BUSY 0x00000008 /**< UART busy */
123#define UART_FR_CTS 0x00000001 /**< Clear to send */
124/** @} */
125/*---------------------------------------------------------------------------*/
126/** \name UART_ILPR Register Bit-Masks
127 * @{
128 */
129#define UART_ILPR_ILPDVSR 0x000000FF /**< IrDA low-power divisor */
130/** @} */
131/*---------------------------------------------------------------------------*/
132/** \name UART_IBRD Register Bit-Masks
133 * @{
134 */
135#define UART_IBRD_DIVINT 0x0000FFFF /**< Integer baud-rate divisor */
136/** @} */
137/*---------------------------------------------------------------------------*/
138/** \name UART_FPRD Register Bit-Masks
139 * @{
140 */
141#define UART_FBRD_DIVFRAC 0x0000003F /**< Fractional baud-rate divisor */
142/** @} */
143/*---------------------------------------------------------------------------*/
144/** \name UART_LCRH Register Bit-Masks
145 * @{
146 */
147#define UART_LCRH_SPS 0x00000080 /**< UART stick parity select */
148#define UART_LCRH_WLEN 0x00000060 /**< UART word length */
149#define UART_LCRH_FEN 0x00000010 /**< UART enable FIFOs */
150#define UART_LCRH_STP2 0x00000008 /**< UART two stop bits select */
151#define UART_LCRH_EPS 0x00000004 /**< UART even parity select */
152#define UART_LCRH_PEN 0x00000002 /**< UART parity enable */
153#define UART_LCRH_BRK 0x00000001 /**< UART send break */
154/** @} */
155/*---------------------------------------------------------------------------*/
156/** \name UART_LCRH_WLEN Values
157 * @{
158 */
159#define UART_LCRH_WLEN_8 0x00000060
160#define UART_LCRH_WLEN_7 0x00000040
161#define UART_LCRH_WLEN_6 0x00000020
162#define UART_LCRH_WLEN_5 0x00000000
163/** @} */
164/*---------------------------------------------------------------------------*/
165/** \name UART_CTL Register Bit-Masks
166 * @{
167 */
168#define UART_CTL_CTSEN 0x00008000 /**< UART CTS flow-control enable (UART1 only) */
169#define UART_CTL_RTSEN 0x00004000 /**< UART RTS flow-control enable (UART1 only) */
170#define UART_CTL_RXE 0x00000200 /**< UART receive enable */
171#define UART_CTL_TXE 0x00000100 /**< UART transmit enable */
172#define UART_CTL_LBE 0x00000080 /**< UART loop back enable */
173#define UART_CTL_LIN 0x00000040 /**< LIN mode enable */
174#define UART_CTL_HSE 0x00000020 /**< High-speed enable */
175#define UART_CTL_EOT 0x00000010 /**< End of transmission */
176#define UART_CTL_SMART 0x00000008 /**< ISO 7816 Smart Card support */
177#define UART_CTL_SIRLP 0x00000004 /**< UART SIR low-power mode */
178#define UART_CTL_SIREN 0x00000002 /**< UART SIR enable */
179#define UART_CTL_UARTEN 0x00000001 /**< UART enable */
180/** @} */
181/*---------------------------------------------------------------------------*/
182/** \name UART_IFLS Register Bit-Masks
183 * @{
184 */
185#define UART_IFLS_RXIFLSEL 0x00000038 /**< UART RX FIFO level select */
186#define UART_IFLS_TXIFLSEL 0x00000007 /**< UART TX FIFO level select */
187/** @} */
188/*---------------------------------------------------------------------------*/
189/** \name UART_IFLS_RXIFLSEL Possible Values
190 * @{
191 */
192#define UART_IFLS_RXIFLSEL_7_8 0x00000020 /**< UART RX FIFO >= 7/8 full */
193#define UART_IFLS_RXIFLSEL_3_4 0x00000018 /**< UART RX FIFO >= 3/4 full */
194#define UART_IFLS_RXIFLSEL_1_2 0x00000010 /**< UART RX FIFO >= 1/2 full */
195#define UART_IFLS_RXIFLSEL_1_4 0x00000008 /**< UART RX FIFO >= 1/4 full */
196#define UART_IFLS_RXIFLSEL_1_8 0x00000000 /**< UART RX FIFO >= 1/8 full */
197/** @} */
198/*---------------------------------------------------------------------------*/
199/** \name UART_IFLS_TXIFLSEL Possible Values
200 * @{
201 */
202#define UART_IFLS_TXIFLSEL_1_8 0x00000004 /**< UART TX FIFO >= 1/8 empty */
203#define UART_IFLS_TXIFLSEL_1_4 0x00000003 /**< UART TX FIFO >= 1/4 empty */
204#define UART_IFLS_TXIFLSEL_1_2 0x00000002 /**< UART TX FIFO >= 1/2 empty */
205#define UART_IFLS_TXIFLSEL_3_4 0x00000001 /**< UART TX FIFO >= 3/4 empty */
206#define UART_IFLS_TXIFLSEL_7_8 0x00000000 /**< UART TX FIFO >= 7/8 empty */
207/** @} */
208/*---------------------------------------------------------------------------*/
209/** \name UART_IM Register Bit-Masks
210 * @{
211 */
212#define UART_IM_LME5IM 0x00008000 /**< LIN mode edge 5 intr mask */
213#define UART_IM_LME1IM 0x00004000 /**< LIN mode edge 1 intr mask */
214#define UART_IM_LMSBIM 0x00002000 /**< LIN mode sync break mask */
215#define UART_IM_NINEBITIM 0x00001000 /**< 9-bit mode interrupt mask */
216#define UART_IM_OEIM 0x00000400 /**< UART overrun error mask */
217#define UART_IM_BEIM 0x00000200 /**< UART break error mask */
218#define UART_IM_PEIM 0x00000100 /**< UART parity error mask */
219#define UART_IM_FEIM 0x00000080 /**< UART framing error */
220#define UART_IM_RTIM 0x00000040 /**< UART receive time-out mask */
221#define UART_IM_TXIM 0x00000020 /**< UART transmit intr mask */
222#define UART_IM_RXIM 0x00000010 /**< UART receive interrupt mask */
223#define UART_IM_CTSIM 0x00000002 /**< UART CTS modem mask */
224/** @} */
225/*---------------------------------------------------------------------------*/
226/** \name UART_RIS Register Bit-Masks
227 * @{
228 */
229#define UART_RIS_LME5RIS 0x00008000 /**< LIN mode edge 5 raw */
230#define UART_RIS_LME1RIS 0x00004000 /**< LIN mode edge 1 raw */
231#define UART_RIS_LMSBRIS 0x00002000 /**< LIN mode sync break raw */
232#define UART_RIS_NINEBITRIS 0x00001000 /**< 9-bit mode raw intr */
233#define UART_RIS_OERIS 0x00000400 /**< UART overrun error raw */
234#define UART_RIS_BERIS 0x00000200 /**< UART break error raw */
235#define UART_RIS_PERIS 0x00000100 /**< UART parity error raw */
236#define UART_RIS_FERIS 0x00000080 /**< UART framing error raw */
237#define UART_RIS_RTRIS 0x00000040 /**< UART RX time-out raw */
238#define UART_RIS_TXRIS 0x00000020 /**< UART transmit raw */
239#define UART_RIS_RXRIS 0x00000010 /**< UART receive raw */
240#define UART_RIS_CTSRIS 0x00000002 /**< UART CTS modem */
241/** @} */
242/*---------------------------------------------------------------------------*/
243/** \name UART_RIS Register Bit-Masks
244 * @{
245 */
246#define UART_MIS_LME5MIS 0x00008000 /**< LIN mode edge 5 masked stat */
247#define UART_MIS_LME1MIS 0x00004000 /**< LIN mode edge 1 masked stat */
248#define UART_MIS_LMSBMIS 0x00002000 /**< LIN mode sync br masked stat */
249#define UART_MIS_NINEBITMIS 0x00001000 /**< 9-bit mode masked stat */
250#define UART_MIS_OEMIS 0x00000400 /**< UART overrun err masked stat */
251#define UART_MIS_BEMIS 0x00000200 /**< UART break err masked stat */
252#define UART_MIS_PEMIS 0x00000100 /**< UART parity err masked stat */
253#define UART_MIS_FEMIS 0x00000080 /**< UART framing err masked stat */
254#define UART_MIS_RTMIS 0x00000040 /**< UART RX time-out masked stat */
255#define UART_MIS_TXMIS 0x00000020 /**< UART TX masked intr stat */
256#define UART_MIS_RXMIS 0x00000010 /**< UART RX masked intr stat */
257#define UART_MIS_CTSMIS 0x00000002 /**< UART CTS modem masked stat */
258/** @} */
259/*---------------------------------------------------------------------------*/
260/** \name UART_ICR Register Bit-Masks
261 * @{
262 */
263#define UART_ICR_LME5IC 0x00008000 /**< LIN mode edge 5 intr clear */
264#define UART_ICR_LME1IC 0x00004000 /**< LIN mode edge 1 intr clear */
265#define UART_ICR_LMSBIC 0x00002000 /**< LIN mode sync br intr clear */
266#define UART_ICR_NINEBITIC 0x00001000 /**< 9-bit mode intr clear */
267#define UART_ICR_OEIC 0x00000400 /**< Overrun error intr clear */
268#define UART_ICR_BEIC 0x00000200 /**< Break error intr clear */
269#define UART_ICR_PEIC 0x00000100 /**< Parity error intr clear */
270#define UART_ICR_FEIC 0x00000080 /**< Framing error intr clear */
271#define UART_ICR_RTIC 0x00000040 /**< Receive time-out intr clear */
272#define UART_ICR_TXIC 0x00000020 /**< Transmit intr clear */
273#define UART_ICR_RXIC 0x00000010 /**< Receive intr clear */
274#define UART_ICR_CTSIC 0x00000002 /**< UART CTS modem intr clear */
275/** @} */
276/*---------------------------------------------------------------------------*/
277/** \name UART_DMACTL Register Bit-Masks
278 * @{
279 */
280#define UART_DMACTL_DMAERR 0x00000004 /**< DMA on error */
281#define UART_DMACTL_TXDMAE 0x00000002 /**< Transmit DMA enable */
282#define UART_DMACTL_RXDMAE 0x00000001 /**< Receive DMA enable */
283/** @} */
284/*---------------------------------------------------------------------------*/
285/** \name UART_LCTL Register Bit-Masks
286 * @{
287 */
288#define UART_LCTL_BLEN 0x00000030 /**< Sync break length */
289#define UART_LCTL_MASTER 0x00000001 /**< LIN master enable */
290/** @} */
291/*---------------------------------------------------------------------------*/
292/** \name UART_LSS Register Bit-Masks
293 * @{
294 */
295#define UART_LSS_TSS 0x0000FFFF /**< Timer snap shot */
296/** @} */
297/*---------------------------------------------------------------------------*/
298/** \name UART_LTIM Register Bit-Masks
299 * @{
300 */
301#define UART_LTIM_TIMER 0x0000FFFF /**< Timer value */
302/** @} */
303/*---------------------------------------------------------------------------*/
304/** \name UART_O_NINEBITADDR Register Bit-Masks
305 * @{
306 */
307#define UART_NINEBITADDR_NINEBITEN 0x00008000 /**< Enable 9-bit mode */
308#define UART_NINEBITADDR_ADDR 0x000000FF /**< Self address for 9-bit mode */
309/** @} */
310/*---------------------------------------------------------------------------*/
311/** \name UART_O_NINEBITADDR Register Bit-Masks
312 * @{
313 */
314#define UART_NINEBITAMASK_RANGE 0x0000FF00 /**< Self addr range, 9-bit mode */
315#define UART_NINEBITAMASK_MASK 0x000000FF /**< Self addr mask, 9-bit mode */
316/** @} */
317/*---------------------------------------------------------------------------*/
318/** \name UART_PP Register Bit-Masks
319 * @{
320 */
321#define UART_PP_NB 0x00000002 /**< 9-bit support */
322#define UART_PP_SC 0x00000001 /**< Smart card support */
323/** @} */
324/*---------------------------------------------------------------------------*/
325/** \name UART_CC Register Bit-Masks
326 * @{
327 */
328#define UART_CC_CS 0x00000007 /**< UART BAUD & sys clock source */
329/** @} */
330/*---------------------------------------------------------------------------*/
331/** \name UART functions
332 * @{
333 */
334
335/** \brief Initialises the UART controller, configures I/O control
336 * and interrupts
337 * \param uart The UART instance to use (0 to \c UART_INSTANCE_COUNT - 1)
338 */
339void uart_init(uint8_t uart);
340
341/** \brief Sends a single character down the UART
342 * \param uart The UART instance to use (0 to \c UART_INSTANCE_COUNT - 1)
343 * \param b The character to transmit
344 */
345void uart_write_byte(uint8_t uart, uint8_t b);
346
347/** \brief Assigns a callback to be called when the UART receives a byte
348 * \param uart The UART instance to use (0 to \c UART_INSTANCE_COUNT - 1)
349 * \param input A pointer to the function
350 */
351void uart_set_input(uint8_t uart, int (* input)(unsigned char c));
352
353/** @} */
354
355#endif /* UART_H_ */
356
357/**
358 * @}
359 * @}
360 */
uart_set_input
void uart_set_input(uint8_t uart, int(*input)(unsigned char c))
Assigns a callback to be called when the UART receives a byte.
Definition uart.c:334
uart_write_byte
void uart_write_byte(uint8_t uart, uint8_t b)
Sends a single character down the UART.
Definition uart.c:344
uart_init
void uart_init(void)
Initializa the UART driver.
Definition uart-arch.c:87