127spu_periph_init_cfg(
void)
131 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_FPU));
132 spu_peripheral_config_non_secure((uint32_t)NRF_FPU,
false);
134 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_REGULATORS));
135 spu_peripheral_config_non_secure((uint32_t)NRF_REGULATORS,
false);
137 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_CLOCK));
138 spu_peripheral_config_non_secure((uint32_t)NRF_CLOCK,
true);
142 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_SPIM0));
143 spu_peripheral_config_non_secure((uint32_t)NRF_SPIM0,
false);
148 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_SPIM1));
149 spu_peripheral_config_non_secure((uint32_t)NRF_SPIM1,
false);
152 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_SPIM4));
153 spu_peripheral_config_non_secure((uint32_t)NRF_SPIM4,
false);
155 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_SPIM2));
156 spu_peripheral_config_non_secure((uint32_t)NRF_SPIM2,
false);
158 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_SPIM3));
159 spu_peripheral_config_non_secure((uint32_t)NRF_SPIM3,
false);
161 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_SAADC));
162 spu_peripheral_config_non_secure((uint32_t)NRF_SAADC,
false);
164 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_TIMER0));
165 spu_peripheral_config_non_secure((uint32_t)NRF_TIMER0,
false);
168 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_TIMER1));
169 spu_peripheral_config_non_secure((uint32_t)NRF_TIMER1,
false);
172 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_TIMER2));
173 spu_peripheral_config_non_secure((uint32_t)NRF_TIMER2,
false);
175 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_RTC0));
176 spu_peripheral_config_non_secure((uint32_t)NRF_RTC0,
false);
179 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_RTC1));
180 spu_peripheral_config_non_secure((uint32_t)NRF_RTC1,
false);
183 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_DPPIC));
184 spu_peripheral_config_non_secure((uint32_t)NRF_DPPIC,
false);
186 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_WDT0));
187 spu_peripheral_config_non_secure((uint32_t)NRF_WDT0,
false);
189 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_WDT1));
190 spu_peripheral_config_non_secure((uint32_t)NRF_WDT1,
false);
192 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_COMP));
193 spu_peripheral_config_non_secure((uint32_t)NRF_COMP,
false);
195 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_EGU0));
196 spu_peripheral_config_non_secure((uint32_t)NRF_EGU0,
false);
198 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_EGU1));
199 spu_peripheral_config_non_secure((uint32_t)NRF_EGU1,
false);
201 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_EGU2));
202 spu_peripheral_config_non_secure((uint32_t)NRF_EGU2,
false);
204 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_EGU3));
205 spu_peripheral_config_non_secure((uint32_t)NRF_EGU3,
false);
207 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_EGU4));
208 spu_peripheral_config_non_secure((uint32_t)NRF_EGU4,
false);
209#ifndef PSA_API_TEST_IPC
212 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_EGU5));
213 spu_peripheral_config_non_secure((uint32_t)NRF_EGU5,
false);
216 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_PWM0));
217 spu_peripheral_config_non_secure((uint32_t)NRF_PWM0,
false);
219 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_PWM1));
220 spu_peripheral_config_non_secure((uint32_t)NRF_PWM1,
false);
222 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_PWM2));
223 spu_peripheral_config_non_secure((uint32_t)NRF_PWM2,
false);
225 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_PWM3));
226 spu_peripheral_config_non_secure((uint32_t)NRF_PWM3,
false);
228 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_PDM0));
229 spu_peripheral_config_non_secure((uint32_t)NRF_PDM0,
false);
231 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_I2S0));
232 spu_peripheral_config_non_secure((uint32_t)NRF_I2S0,
false);
234 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_IPC));
235 spu_peripheral_config_non_secure((uint32_t)NRF_IPC,
false);
237 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_QSPI));
238 spu_peripheral_config_non_secure((uint32_t)NRF_QSPI,
false);
240 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_NFCT));
241 spu_peripheral_config_non_secure((uint32_t)NRF_NFCT,
false);
243 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_GPIOTE1_NS));
244 spu_peripheral_config_non_secure((uint32_t)NRF_GPIOTE1_NS,
false);
246 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_MUTEX));
247 spu_peripheral_config_non_secure((uint32_t)NRF_MUTEX,
false);
249 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_QDEC0));
250 spu_peripheral_config_non_secure((uint32_t)NRF_QDEC0,
false);
252 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_QDEC1));
253 spu_peripheral_config_non_secure((uint32_t)NRF_QDEC1,
false);
255 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_USBD));
256 spu_peripheral_config_non_secure((uint32_t)NRF_USBD,
false);
258 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_USBREGULATOR));
259 spu_peripheral_config_non_secure((uint32_t)NRF_USBREGULATOR,
false);
261 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_NVMC));
262 spu_peripheral_config_non_secure((uint32_t)NRF_NVMC,
false);
264 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_P0));
265 spu_peripheral_config_non_secure((uint32_t)NRF_P0,
false);
267 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_P1));
268 spu_peripheral_config_non_secure((uint32_t)NRF_P1,
false);
270 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_VMC));
271 spu_peripheral_config_non_secure((uint32_t)NRF_VMC,
false);
274 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_UARTE1));
275 spu_peripheral_config_non_secure((uint32_t)NRF_UARTE1,
false);
279 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_UARTE2));
280 spu_peripheral_config_non_secure((uint32_t)NRF_UARTE2,
false);
282 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_TWIM2));
283 spu_peripheral_config_non_secure((uint32_t)NRF_TWIM2,
false);
285 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_IPC_S));
286 spu_peripheral_config_non_secure((uint32_t)NRF_IPC_S,
false);
288 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_VMC_S));
289 spu_peripheral_config_non_secure((uint32_t)NRF_VMC_S,
false);
291 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_FPU_S));
292 spu_peripheral_config_non_secure((uint32_t)NRF_FPU_S,
false);
294 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_EGU1_S));
295 spu_peripheral_config_non_secure((uint32_t)NRF_EGU1_S,
false);
297 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_EGU2_S));
298 spu_peripheral_config_non_secure((uint32_t)NRF_EGU2_S,
false);
300 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_DPPIC_S));
301 spu_peripheral_config_non_secure((uint32_t)NRF_DPPIC_S,
false);
303 NVIC_DisableIRQ(NRFX_IRQ_NUMBER_GET(NRF_REGULATORS_S));
304 spu_peripheral_config_non_secure((uint32_t)NRF_REGULATORS_S,
false);
307 spu_dppi_config_non_secure(
false);
310 spu_gpio_config_non_secure(0,
true);
311 spu_gpio_config_non_secure(1,
true);
319 nrf_gpio_pin_mcu_select(PIN_XL1, NRF_GPIO_PIN_MCUSEL_PERIPHERAL);
320 nrf_gpio_pin_mcu_select(PIN_XL2, NRF_GPIO_PIN_MCUSEL_PERIPHERAL);
326 NRF_CACHE->ENABLE = CACHE_ENABLE_ENABLE_Enabled;
328 return TFM_PLAT_ERR_SUCCESS;