Contiki-NG
Loading...
Searching...
No Matches
region_defs.h
1/*
2 * Copyright (c) 2017-2020 Arm Limited. All rights reserved.
3 * Copyright (c) 2020 Nordic Semiconductor ASA. All rights reserved.
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 */
17
18/* This file has been modified for use in the Contiki-NG operating system. */
19
20#ifndef __REGION_DEFS_H__
21#define __REGION_DEFS_H__
22
23#include "flash_layout.h"
24
25#define BL2_HEAP_SIZE (0x00001000)
26#define BL2_MSP_STACK_SIZE (0x00001800)
27
28#define S_HEAP_SIZE (0x00001000)
29#define S_MSP_STACK_SIZE_INIT (0x00000400)
30#define S_MSP_STACK_SIZE (0x00000800)
31#define S_PSP_STACK_SIZE (0x00000800)
32
33#define NS_HEAP_SIZE (0x00001000)
34#define NS_MSP_STACK_SIZE (0x000000A0)
35#define NS_PSP_STACK_SIZE (0x00000140)
36
37#define NS_ROM_LIMIT_ADDR (0x7ffff)
38/* Size of nRF SPU (Nordic IDAU) regions */
39#define SPU_FLASH_REGION_SIZE (0x00004000)
40#define SPU_SRAM_REGION_SIZE (0x00002000)
41
42/* This size of buffer is big enough to store an attestation
43 * token produced by initial attestation service
44 */
45#define PSA_INITIAL_ATTEST_TOKEN_MAX_SIZE (0x250)
46
47/*
48 * SPU flash region granularity is 16 KB on nRF5340. Alignment
49 * of partitions is defined in accordance with this constraint.
50 */
51#ifdef BL2
52#ifndef LINK_TO_SECONDARY_PARTITION
53#define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET)
54#define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET)
55#else
56#define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET)
57#define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET)
58#endif /* !LINK_TO_SECONDARY_PARTITION */
59#else
60#define S_IMAGE_PRIMARY_PARTITION_OFFSET (0x0)
61#endif /* BL2 */
62
63#ifndef LINK_TO_SECONDARY_PARTITION
64#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET \
65 + FLASH_S_PARTITION_SIZE)
66#else
67#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET \
68 + FLASH_S_PARTITION_SIZE)
69#endif /* !LINK_TO_SECONDARY_PARTITION */
70
71/* Boot partition structure if MCUBoot is used:
72 * 0x0_0000 Bootloader header
73 * 0x0_0400 Image area
74 * 0x0_FC00 Trailer
75 */
76/* IMAGE_CODE_SIZE is the space available for the software binary image.
77 * It is less than the FLASH_S_PARTITION_SIZE + FLASH_NS_PARTITION_SIZE
78 * because we reserve space for the image header and trailer introduced
79 * by the bootloader.
80 */
81#ifdef BL2
82#define BL2_HEADER_SIZE (0x400) /* 1 KB */
83#define BL2_TRAILER_SIZE (0x400) /* 1 KB */
84#else
85#define BL2_HEADER_SIZE (0x0)
86#define BL2_TRAILER_SIZE (0x0)
87#endif /* BL2 */
88
89#define IMAGE_S_CODE_SIZE \
90 (FLASH_S_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
91#define IMAGE_NS_CODE_SIZE \
92 (FLASH_NS_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
93
94/* Alias definitions for secure and non-secure areas*/
95#define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + (x))
96#define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x))
97
98#define S_RAM_ALIAS(x) (S_RAM_ALIAS_BASE + (x))
99#define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + (x))
100
101/* Secure regions */
102#define S_IMAGE_PRIMARY_AREA_OFFSET \
103 (S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
104#define S_CODE_START (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET))
105#define S_CODE_SIZE (IMAGE_S_CODE_SIZE)
106#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1)
107
108#define S_DATA_START (S_RAM_ALIAS(0x0))
109#define S_DATA_SIZE (TOTAL_RAM_SIZE / 2)
110#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1)
111
112/* The CMSE veneers shall be placed in an NSC region
113 * which will be placed in a secure SPU region with the given alignment.
114 */
115#define CMSE_VENEER_REGION_SIZE (0x400)
116/* The Nordic IDAU has different alignment requirements than the ARM SAU, so
117 * these override the default start and end alignments. */
118#define CMSE_VENEER_REGION_START_ALIGN \
119 (ALIGN(SPU_FLASH_REGION_SIZE) - CMSE_VENEER_REGION_SIZE + \
120 (. > (ALIGN(SPU_FLASH_REGION_SIZE) - CMSE_VENEER_REGION_SIZE) \
121 ? SPU_FLASH_REGION_SIZE : 0))
122#define CMSE_VENEER_REGION_END_ALIGN (ALIGN(SPU_FLASH_REGION_SIZE))
123/* We want the veneers placed in the secure code so it isn't placed at the very
124 * end. When placed in code, we don't need an absolute start address. */
125#define CMSE_VENEER_REGION_IN_CODE
126
127/* Non-secure regions */
128#define NS_IMAGE_PRIMARY_AREA_OFFSET \
129 (NS_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
130#define NS_CODE_START (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_AREA_OFFSET))
131#define NS_CODE_SIZE (IMAGE_NS_CODE_SIZE)
132#define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1)
133
134#define NS_DATA_START (NS_RAM_ALIAS(S_DATA_SIZE))
135#ifdef PSA_API_TEST_IPC
136/* Last SRAM region must be kept secure for PSA FF tests */
137#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE - SPU_SRAM_REGION_SIZE)
138#else
139#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE)
140#endif
141#define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE - 1)
142
143/* NS partition information is used for SPU configuration */
144#define NS_PARTITION_START \
145 (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_PARTITION_OFFSET))
146#define NS_PARTITION_SIZE (FLASH_NS_PARTITION_SIZE)
147
148/* Secondary partition for new images in case of firmware upgrade */
149#define SECONDARY_PARTITION_START \
150 (NS_ROM_ALIAS(S_IMAGE_SECONDARY_PARTITION_OFFSET))
151#define SECONDARY_PARTITION_SIZE (FLASH_S_PARTITION_SIZE + \
152 FLASH_NS_PARTITION_SIZE)
153
154#ifdef BL2
155/* Bootloader regions */
156#define BL2_CODE_START (S_ROM_ALIAS(FLASH_AREA_BL2_OFFSET))
157#define BL2_CODE_SIZE (FLASH_AREA_BL2_SIZE)
158#define BL2_CODE_LIMIT (BL2_CODE_START + BL2_CODE_SIZE - 1)
159
160#define BL2_DATA_START (S_RAM_ALIAS(0x0))
161#define BL2_DATA_SIZE (TOTAL_RAM_SIZE)
162#define BL2_DATA_LIMIT (BL2_DATA_START + BL2_DATA_SIZE - 1)
163#endif /* BL2 */
164
165/* Shared data area between bootloader and runtime firmware.
166 * Shared data area is allocated at the beginning of the RAM, it is overlapping
167 * with TF-M Secure code's MSP stack
168 */
169#define BOOT_TFM_SHARED_DATA_BASE S_RAM_ALIAS_BASE
170#define BOOT_TFM_SHARED_DATA_SIZE (0x400)
171#define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + \
172 BOOT_TFM_SHARED_DATA_SIZE - 1)
173
174/* Regions used by psa-arch-tests to keep state */
175#define PSA_TEST_SCRATCH_AREA_SIZE (0x400)
176
177#ifdef PSA_API_TEST_IPC
178/* Firmware Framework test suites */
179#define FF_TEST_PARTITION_SIZE 0x100
180#define PSA_TEST_SCRATCH_AREA_BASE (NS_DATA_LIMIT + 1 - \
181 PSA_TEST_SCRATCH_AREA_SIZE - \
182 FF_TEST_PARTITION_SIZE)
183
184/* The psa-arch-tests implementation requires that the test partitions are
185 * placed in this specific order:
186 * TEST_NSPE_MMIO < TEST_SERVER < TEST_DRIVER
187 *
188 * TEST_NSPE_MMIO region must be in the NSPE, while TEST_SERVER and TEST_DRIVER
189 * must be in SPE.
190 *
191 * The TEST_NSPE_MMIO region is defined in the psa-arch-tests implementation,
192 * and it should be placed at the end of the NSPE area, after
193 * PSA_TEST_SCRATCH_AREA.
194 */
195#define FF_TEST_SERVER_PARTITION_MMIO_START (NS_DATA_LIMIT + 1)
196#define FF_TEST_SERVER_PARTITION_MMIO_END (FF_TEST_SERVER_PARTITION_MMIO_START + \
197 FF_TEST_PARTITION_SIZE - 1)
198#define FF_TEST_DRIVER_PARTITION_MMIO_START (FF_TEST_SERVER_PARTITION_MMIO_END + 1)
199#define FF_TEST_DRIVER_PARTITION_MMIO_END (FF_TEST_DRIVER_PARTITION_MMIO_START + \
200 FF_TEST_PARTITION_SIZE - 1)
201#else
202/* Development APIs test suites */
203#define PSA_TEST_SCRATCH_AREA_BASE (NS_DATA_LIMIT + 1 - \
204 PSA_TEST_SCRATCH_AREA_SIZE)
205#endif /* PSA_API_TEST_IPC */
206
207#endif /* __REGION_DEFS_H__ */