Contiki-NG
|
Files | |
file | gpio.c |
Implementation of the cc2538 GPIO controller. | |
file | gpio.h |
Header file with register and macro declarations for the cc2538 GPIO module. | |
Functions | |
static void | gpio_port_isr (uint8_t port) |
Interrupt service routine for Port port. | |
Numeric representation of the four GPIO ports | |
#define | GPIO_A_NUM 0 |
GPIO_A: 0. | |
#define | GPIO_B_NUM 1 |
GPIO_B: 1. | |
#define | GPIO_C_NUM 2 |
GPIO_C: 2. | |
#define | GPIO_D_NUM 3 |
GPIO_D: 3. | |
GPIO Manipulation macros | |
#define | GPIO_SET_INPUT(PORT_BASE, PIN_MASK) do { REG((PORT_BASE) + GPIO_DIR) &= ~(PIN_MASK); } while(0) |
Set pins with PIN_MASK of port with PORT_BASE to input. | |
#define | GPIO_SET_OUTPUT(PORT_BASE, PIN_MASK) do { REG((PORT_BASE) + GPIO_DIR) |= (PIN_MASK); } while(0) |
Set pins with PIN_MASK of port with PORT_BASE to output. | |
#define | GPIO_IS_OUTPUT(PORT_BASE, PIN_MASK) (REG((PORT_BASE) + GPIO_DIR) & (PIN_MASK)) |
Return whether pins with PIN_MASK of port with PORT_BASE are set to output. | |
#define | GPIO_SET_PIN(PORT_BASE, PIN_MASK) do { REG((PORT_BASE) + GPIO_DATA + ((PIN_MASK) << 2)) = 0xFF; } while(0) |
Set pins with PIN_MASK of port with PORT_BASE high. | |
#define | GPIO_CLR_PIN(PORT_BASE, PIN_MASK) do { REG((PORT_BASE) + GPIO_DATA + ((PIN_MASK) << 2)) = 0x00; } while(0) |
Set pins with PIN_MASK of port with PORT_BASE low. | |
#define | GPIO_WRITE_PIN(PORT_BASE, PIN_MASK, value) do { REG((PORT_BASE) + GPIO_DATA + ((PIN_MASK) << 2)) = (value); } while(0) |
Set pins with PIN_MASK of port with PORT_BASE to value. | |
#define | GPIO_READ_PIN(PORT_BASE, PIN_MASK) REG((PORT_BASE) + GPIO_DATA + ((PIN_MASK) << 2)) |
Read pins with PIN_MASK of port with PORT_BASE. | |
#define | GPIO_DETECT_EDGE(PORT_BASE, PIN_MASK) do { REG((PORT_BASE) + GPIO_IS) &= ~(PIN_MASK); } while(0) |
Set pins with PIN_MASK of port with PORT_BASE to detect edge. | |
#define | GPIO_DETECT_LEVEL(PORT_BASE, PIN_MASK) do { REG((PORT_BASE) + GPIO_IS) |= (PIN_MASK); } while(0) |
Set pins with PIN_MASK of port with PORT_BASE to detect level. | |
#define | GPIO_TRIGGER_BOTH_EDGES(PORT_BASE, PIN_MASK) do { REG((PORT_BASE) + GPIO_IBE) |= (PIN_MASK); } while(0) |
Set pins with PIN_MASK of port with PORT_BASE to trigger an interrupt on both edges. | |
#define | GPIO_TRIGGER_SINGLE_EDGE(PORT_BASE, PIN_MASK) do { REG((PORT_BASE) + GPIO_IBE) &= ~(PIN_MASK); } while(0) |
Set pins with PIN_MASK of port with PORT_BASE to trigger an interrupt on single edge (controlled by GPIO_IEV). | |
#define | GPIO_DETECT_RISING(PORT_BASE, PIN_MASK) do { REG((PORT_BASE) + GPIO_IEV) |= (PIN_MASK); } while(0) |
Set pins with PIN_MASK of port with PORT_BASE to trigger an interrupt on rising edge. | |
#define | GPIO_DETECT_FALLING(PORT_BASE, PIN_MASK) do { REG((PORT_BASE) + GPIO_IEV) &= ~(PIN_MASK); } while(0) |
Set pins with PIN_MASK of port with PORT_BASE to trigger an interrupt on falling edge. | |
#define | GPIO_ENABLE_INTERRUPT(PORT_BASE, PIN_MASK) do { REG((PORT_BASE) + GPIO_IE) |= (PIN_MASK); } while(0) |
Enable interrupt triggering for pins with PIN_MASK of port with PORT_BASE. | |
#define | GPIO_DISABLE_INTERRUPT(PORT_BASE, PIN_MASK) do { REG((PORT_BASE) + GPIO_IE) &= ~(PIN_MASK); } while(0) |
Disable interrupt triggering for pins with PIN_MASK of port with PORT_BASE. | |
#define | GPIO_GET_RAW_INT_STATUS(PORT_BASE) REG((PORT_BASE) + GPIO_RIS) |
Get raw interrupt status of port with PORT_BASE. | |
#define | GPIO_GET_MASKED_INT_STATUS(PORT_BASE) REG((PORT_BASE) + GPIO_MIS) |
Get masked interrupt status of port with PORT_BASE. | |
#define | GPIO_CLEAR_INTERRUPT(PORT_BASE, PIN_MASK) do { REG((PORT_BASE) + GPIO_IC) = (PIN_MASK); } while(0) |
Clear interrupt triggering for pins with PIN_MASK of port with PORT_BASE. | |
#define | GPIO_PERIPHERAL_CONTROL(PORT_BASE, PIN_MASK) do { REG((PORT_BASE) + GPIO_AFSEL) |= (PIN_MASK); } while(0) |
Configure the pin to be under peripheral control with PIN_MASK of port with PORT_BASE. | |
#define | GPIO_SOFTWARE_CONTROL(PORT_BASE, PIN_MASK) do { REG((PORT_BASE) + GPIO_AFSEL) &= ~(PIN_MASK); } while(0) |
Configure the pin to be software controlled with PIN_MASK of port with PORT_BASE. | |
#define | GPIO_POWER_UP_ON_RISING(PORT, PIN_MASK) |
Set pins with PIN_MASK of port PORT to trigger a power-up interrupt on rising edge. | |
#define | GPIO_POWER_UP_ON_FALLING(PORT, PIN_MASK) |
Set pins with PIN_MASK of port PORT to trigger a power-up interrupt on falling edge. | |
#define | GPIO_ENABLE_POWER_UP_INTERRUPT(PORT, PIN_MASK) |
Enable power-up interrupt triggering for pins with PIN_MASK of port PORT. | |
#define | GPIO_DISABLE_POWER_UP_INTERRUPT(PORT, PIN_MASK) |
Disable power-up interrupt triggering for pins with PIN_MASK of port PORT. | |
#define | GPIO_GET_POWER_UP_INT_STATUS(PORT) ((REG(GPIO_PORT_TO_BASE(PORT) + GPIO_IRQ_DETECT_ACK) >> ((PORT) << 3)) & 0xFF) |
Get power-up interrupt status of port PORT. | |
#define | GPIO_CLEAR_POWER_UP_INTERRUPT(PORT, PIN_MASK) |
Clear power-up interrupt triggering for pins with PIN_MASK of port PORT. | |
#define | GPIO_PIN_MASK(PIN) (1 << (PIN)) |
Converts a pin number to a pin mask. | |
#define | GPIO_PORT_TO_BASE(PORT) (GPIO_A_BASE + ((PORT) << 12)) |
Converts a port number to the port base address. | |
#define | GPIO_PORT_PIN_TO_GPIO_HAL_PIN(PORT, PIN) (((PORT) << 3) + (PIN)) |
Converts a port/pin pair to GPIO HAL pin number. | |
GPIO_DATA register bit masks | |
#define | GPIO_DATA_DATA 0x000000FF |
Input and output data. | |
GPIO_DIR register bit masks | |
#define | GPIO_DIR_DIR 0x000000FF |
Pin Input (0) / Output (1) | |
GPIO_IS register bit masks | |
#define | GPIO_IS_IS 0x000000FF |
Detect Edge (0) / Level (1) | |
GPIO_IBE register bit masks | |
#define | GPIO_IBE_IBE 0x000000FF |
Both Edges (1) / Single (0) | |
GPIO_IEV register bit masks | |
#define | GPIO_IEV_IEV 0x000000FF |
Rising (1) / Falling (0) | |
GPIO_IE register bit masks | |
#define | GPIO_IE_IE 0x000000FF |
Masked (0) / Not Masked (1) | |
GPIO_RIS register bit masks | |
#define | GPIO_RIS_RIS 0x000000FF |
Raw interrupt status. | |
GPIO_MIS register bit masks | |
#define | GPIO_MIS_MIS 0x000000FF |
Masked interrupt status. | |
GPIO_IC register bit masks | |
#define | GPIO_IC_IC 0x000000FF |
Clear edge detection (1) | |
GPIO_AFSEL register bit masks | |
#define | GPIO_AFSEL_AFSEL 0x000000FF |
Software (0) / Peripheral (1) | |
GPIO_GPIOLOCK register bit masks | |
#define | GPIO_GPIOLOCK_LOCK 0xFFFFFFFF |
Locked (1) / Unlocked (0) | |
GPIO_GPIOCR register bit masks | |
#define | GPIO_GPIOCR_CR 0x000000FF |
Allow alternate function (1) | |
GPIO_USB_CTRL register bit masks | |
#define | GPIO_USB_CTRL_USB_EDGE_CTL 0x00000001 |
Rising (0) / Falling (1) | |
GPIO_USB_IRQ_ACK register bit masks | |
#define | GPIO_USB_IRQ_ACK_USBACK 0x00000001 |
Detected (1) / Not detected (0) | |
Driver for the cc2538 GPIO controller
#define GPIO_CLEAR_INTERRUPT | ( | PORT_BASE, | |
PIN_MASK ) do { REG((PORT_BASE) + GPIO_IC) = (PIN_MASK); } while(0) |
Clear interrupt triggering for pins with PIN_MASK of port with PORT_BASE.
PORT_BASE | GPIO Port register offset |
PIN_MASK | Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80 |
Definition at line 242 of file gpio.h.
Referenced by gpio_port_isr().
#define GPIO_CLEAR_POWER_UP_INTERRUPT | ( | PORT, | |
PIN_MASK ) |
Clear power-up interrupt triggering for pins with PIN_MASK of port PORT.
PORT | GPIO Port (not port base address) |
PIN_MASK | Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80 |
Definition at line 310 of file gpio.h.
Referenced by gpio_port_isr().
#define GPIO_CLR_PIN | ( | PORT_BASE, | |
PIN_MASK ) do { REG((PORT_BASE) + GPIO_DATA + ((PIN_MASK) << 2)) = 0x00; } while(0) |
Set pins with PIN_MASK of port with PORT_BASE low.
PORT_BASE | GPIO Port register offset |
PIN_MASK | Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80 |
Definition at line 113 of file gpio.h.
Referenced by antenna_select_at86rf215(), antenna_select_cc2538(), dht22_read(), gpio_hal_arch_no_port_clear_pins(), mmc_arch_get_cd(), mp3_wtv020sd_gpio_next(), mp3_wtv020sd_gpio_play(), mp3_wtv020sd_reset(), pm_init(), and pwm_stop().
#define GPIO_DETECT_EDGE | ( | PORT_BASE, | |
PIN_MASK ) do { REG((PORT_BASE) + GPIO_IS) &= ~(PIN_MASK); } while(0) |
Set pins with PIN_MASK of port with PORT_BASE to detect edge.
PORT_BASE | GPIO Port register offset |
PIN_MASK | Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80 |
Definition at line 154 of file gpio.h.
Referenced by gpio_hal_arch_no_port_pin_cfg_set(), and rtcc_init().
#define GPIO_DETECT_FALLING | ( | PORT_BASE, | |
PIN_MASK ) do { REG((PORT_BASE) + GPIO_IEV) &= ~(PIN_MASK); } while(0) |
Set pins with PIN_MASK of port with PORT_BASE to trigger an interrupt on falling edge.
PORT_BASE | GPIO Port register offset |
PIN_MASK | Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80 |
Definition at line 193 of file gpio.h.
Referenced by gpio_hal_arch_no_port_pin_cfg_set(), and rtcc_init().
#define GPIO_DETECT_LEVEL | ( | PORT_BASE, | |
PIN_MASK ) do { REG((PORT_BASE) + GPIO_IS) |= (PIN_MASK); } while(0) |
#define GPIO_DETECT_RISING | ( | PORT_BASE, | |
PIN_MASK ) do { REG((PORT_BASE) + GPIO_IEV) |= (PIN_MASK); } while(0) |
Set pins with PIN_MASK of port with PORT_BASE to trigger an interrupt on rising edge.
PORT_BASE | GPIO Port register offset |
PIN_MASK | Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80 |
Definition at line 185 of file gpio.h.
Referenced by gpio_hal_arch_no_port_pin_cfg_set().
#define GPIO_DISABLE_INTERRUPT | ( | PORT_BASE, | |
PIN_MASK ) do { REG((PORT_BASE) + GPIO_IE) &= ~(PIN_MASK); } while(0) |
Disable interrupt triggering for pins with PIN_MASK of port with PORT_BASE.
PORT_BASE | GPIO Port register offset |
PIN_MASK | Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80 |
Definition at line 209 of file gpio.h.
Referenced by gpio_hal_arch_no_port_pin_cfg_set().
#define GPIO_DISABLE_POWER_UP_INTERRUPT | ( | PORT, | |
PIN_MASK ) |
Disable power-up interrupt triggering for pins with PIN_MASK of port PORT.
PORT | GPIO Port (not port base address) |
PIN_MASK | Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80 |
#define GPIO_ENABLE_INTERRUPT | ( | PORT_BASE, | |
PIN_MASK ) do { REG((PORT_BASE) + GPIO_IE) |= (PIN_MASK); } while(0) |
Enable interrupt triggering for pins with PIN_MASK of port with PORT_BASE.
PORT_BASE | GPIO Port register offset |
PIN_MASK | Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80 |
Definition at line 201 of file gpio.h.
Referenced by gpio_hal_arch_no_port_pin_cfg_set(), and rtcc_set_alarm_time_date().
#define GPIO_ENABLE_POWER_UP_INTERRUPT | ( | PORT, | |
PIN_MASK ) |
Enable power-up interrupt triggering for pins with PIN_MASK of port PORT.
PORT | GPIO Port (not port base address) |
PIN_MASK | Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80 |
#define GPIO_GET_MASKED_INT_STATUS | ( | PORT_BASE | ) | REG((PORT_BASE) + GPIO_MIS) |
Get masked interrupt status of port with PORT_BASE.
PORT_BASE | GPIO Port register offset |
The bits set in the returned bit-mask reflect the status of input lines triggering an interrupt. The bits cleared indicate that either no interrupt has been generated, or the interrupt is masked. This is the state of the interrupt after interrupt masking.
Definition at line 234 of file gpio.h.
Referenced by gpio_port_isr().
#define GPIO_GET_POWER_UP_INT_STATUS | ( | PORT | ) | ((REG(GPIO_PORT_TO_BASE(PORT) + GPIO_IRQ_DETECT_ACK) >> ((PORT) << 3)) & 0xFF) |
Get power-up interrupt status of port PORT.
PORT | GPIO Port (not port base address) |
Definition at line 302 of file gpio.h.
Referenced by gpio_port_isr().
#define GPIO_GET_RAW_INT_STATUS | ( | PORT_BASE | ) | REG((PORT_BASE) + GPIO_RIS) |
Get raw interrupt status of port with PORT_BASE.
PORT_BASE | GPIO Port register offset |
The bits set in the returned bit-mask reflect the status of the interrupts trigger conditions detected (raw, before interrupt masking), indicating that all the requirements are met, before they are finally allowed to trigger by the interrupt mask. The bits cleared indicate that corresponding input pins have not initiated an interrupt.
#define GPIO_IS_OUTPUT | ( | PORT_BASE, | |
PIN_MASK ) (REG((PORT_BASE) + GPIO_DIR) & (PIN_MASK)) |
Return whether pins with PIN_MASK of port with PORT_BASE are set to output.
PORT_BASE | GPIO Port register offset |
PIN_MASK | Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80 |
This macro will not return 0 or 1. Instead, it will return the directions of the pins specified by PIN_MASK ORed together. Thus, if 0xC3 (0x80 | 0x40 | 0x02 | 0x01) is passed as the PIN_MASK and pins 7 and 0 are set to output, the macro will return 0x81.
Definition at line 99 of file gpio.h.
Referenced by mmc_arch_get_cd().
#define GPIO_PERIPHERAL_CONTROL | ( | PORT_BASE, | |
PIN_MASK ) do { REG((PORT_BASE) + GPIO_AFSEL) |= (PIN_MASK); } while(0) |
Configure the pin to be under peripheral control with PIN_MASK of port with PORT_BASE.
PORT_BASE | GPIO Port register offset |
PIN_MASK | Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80 |
Definition at line 250 of file gpio.h.
Referenced by i2c_init(), pwm_start(), spi_arch_lock_and_open(), spix_init(), and uart_init().
#define GPIO_PIN_MASK | ( | PIN | ) | (1 << (PIN)) |
Converts a pin number to a pin mask.
PIN | The pin number in the range [0..7] |
Definition at line 320 of file gpio.h.
Referenced by board_init(), gpio_hal_arch_no_port_pin_cfg_get(), gpio_hal_arch_no_port_pin_cfg_set(), i2c_init(), pwm_disable(), pwm_start(), pwm_stop(), spi_arch_lock_and_open(), spix_cs_init(), spix_init(), sys_ctrl_init(), and uart_init().
#define GPIO_PORT_PIN_TO_GPIO_HAL_PIN | ( | PORT, | |
PIN ) (((PORT) << 3) + (PIN)) |
#define GPIO_PORT_TO_BASE | ( | PORT | ) | (GPIO_A_BASE + ((PORT) << 12)) |
Converts a port number to the port base address.
PORT | The port number in the range 0 - 3. Likely GPIO_X_NUM. |
Definition at line 328 of file gpio.h.
Referenced by board_init(), gpio_port_isr(), i2c_init(), pwm_disable(), pwm_start(), pwm_stop(), spi_arch_lock_and_open(), spix_cs_init(), spix_init(), sys_ctrl_init(), and uart_init().
#define GPIO_POWER_UP_ON_FALLING | ( | PORT, | |
PIN_MASK ) |
Set pins with PIN_MASK of port PORT to trigger a power-up interrupt on falling edge.
PORT | GPIO Port (not port base address) |
PIN_MASK | Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80 |
#define GPIO_POWER_UP_ON_RISING | ( | PORT, | |
PIN_MASK ) |
Set pins with PIN_MASK of port PORT to trigger a power-up interrupt on rising edge.
PORT | GPIO Port (not port base address) |
PIN_MASK | Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80 |
#define GPIO_READ_PIN | ( | PORT_BASE, | |
PIN_MASK ) REG((PORT_BASE) + GPIO_DATA + ((PIN_MASK) << 2)) |
Read pins with PIN_MASK of port with PORT_BASE.
PORT_BASE | GPIO Port register offset |
PIN_MASK | Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80 |
This macro will not return 0 or 1. Instead, it will return the values of the pins specified by PIN_MASK ORd together. Thus, if you pass 0xC3 (0x80 | 0x40 | 0x02 | 0x01) as the PIN_MASK and pins 7 and 0 are high, the macro will return 0x81.
Definition at line 147 of file gpio.h.
Referenced by antenna_sw_get(), dht22_read(), gpio_hal_arch_no_port_read_pins(), led_strip_get(), mmc_arch_get_cd(), and mp3_wtv020sd_busy().
#define GPIO_SET_INPUT | ( | PORT_BASE, | |
PIN_MASK ) do { REG((PORT_BASE) + GPIO_DIR) &= ~(PIN_MASK); } while(0) |
Set pins with PIN_MASK of port with PORT_BASE to input.
PORT_BASE | GPIO Port register offset |
PIN_MASK | Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80 |
Definition at line 78 of file gpio.h.
Referenced by board_init(), configure(), dht22_read(), i2c_init(), mp3_wtv020sd_config(), pwm_disable(), rtcc_init(), sys_ctrl_init(), and tps62730_init().
#define GPIO_SET_OUTPUT | ( | PORT_BASE, | |
PIN_MASK ) do { REG((PORT_BASE) + GPIO_DIR) |= (PIN_MASK); } while(0) |
Set pins with PIN_MASK of port with PORT_BASE to output.
PORT_BASE | GPIO Port register offset |
PIN_MASK | Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80 |
Definition at line 85 of file gpio.h.
Referenced by antenna_init(), antenna_sw_config(), dht22_read(), led_strip_config(), mmc_arch_get_cd(), mp3_wtv020sd_config(), pm_init(), pwm_stop(), spi_arch_lock_and_open(), spix_cs_init(), and tps62730_init().
#define GPIO_SET_PIN | ( | PORT_BASE, | |
PIN_MASK ) do { REG((PORT_BASE) + GPIO_DATA + ((PIN_MASK) << 2)) = 0xFF; } while(0) |
Set pins with PIN_MASK of port with PORT_BASE high.
PORT_BASE | GPIO Port register offset |
PIN_MASK | Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80 |
Definition at line 106 of file gpio.h.
Referenced by antenna_select_at86rf215(), antenna_select_cc2538(), dht22_read(), gpio_hal_arch_no_port_set_pins(), led_strip_config(), mp3_wtv020sd_config(), mp3_wtv020sd_gpio_next(), mp3_wtv020sd_gpio_stop(), mp3_wtv020sd_reset(), pwm_stop(), spi_arch_lock_and_open(), and spix_cs_init().
#define GPIO_SOFTWARE_CONTROL | ( | PORT_BASE, | |
PIN_MASK ) do { REG((PORT_BASE) + GPIO_AFSEL) &= ~(PIN_MASK); } while(0) |
Configure the pin to be software controlled with PIN_MASK of port with PORT_BASE.
PORT_BASE | GPIO Port register offset |
PIN_MASK | Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80 |
Definition at line 258 of file gpio.h.
Referenced by antenna_init(), antenna_sw_config(), board_init(), configure(), gpio_hal_arch_no_port_pin_cfg_set(), led_strip_config(), mp3_wtv020sd_config(), pm_enable(), pm_init(), pwm_disable(), pwm_stop(), rtcc_init(), spi_arch_lock_and_open(), spix_cs_init(), and sys_ctrl_init().
#define GPIO_TRIGGER_BOTH_EDGES | ( | PORT_BASE, | |
PIN_MASK ) do { REG((PORT_BASE) + GPIO_IBE) |= (PIN_MASK); } while(0) |
Set pins with PIN_MASK of port with PORT_BASE to trigger an interrupt on both edges.
PORT_BASE | GPIO Port register offset |
PIN_MASK | Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80 |
Definition at line 169 of file gpio.h.
Referenced by gpio_hal_arch_no_port_pin_cfg_set().
#define GPIO_TRIGGER_SINGLE_EDGE | ( | PORT_BASE, | |
PIN_MASK ) do { REG((PORT_BASE) + GPIO_IBE) &= ~(PIN_MASK); } while(0) |
Set pins with PIN_MASK of port with PORT_BASE to trigger an interrupt on single edge (controlled by GPIO_IEV).
PORT_BASE | GPIO Port register offset |
PIN_MASK | Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80 |
Definition at line 177 of file gpio.h.
Referenced by gpio_hal_arch_no_port_pin_cfg_set(), and rtcc_init().
#define GPIO_WRITE_PIN | ( | PORT_BASE, | |
PIN_MASK, | |||
value ) do { REG((PORT_BASE) + GPIO_DATA + ((PIN_MASK) << 2)) = (value); } while(0) |
Set pins with PIN_MASK of port with PORT_BASE to value.
PORT_BASE | GPIO Port register offset |
PIN_MASK | Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80 |
value | The new value to write to the register. Only pins specified by PIN_MASK will be set. |
Thus, if you only want to set a single pin (e.g. pin 2), do not pass 1, but you must pass 0x04 instead (1 << 2). This may seem counter-intuitive at first glance, but it allows a single invocation of this macro to set multiple pins in one go if so desired. For example, you can set pins 3 and 1 and the same time clear pins 2 and 0. To do so, pass 0x0F as the PIN_MASK and then use 0x0A as the value ((1 << 3) | (1 << 1) for pins 3 and 1)
Definition at line 134 of file gpio.h.
Referenced by antenna_sw_config(), antenna_sw_select(), gpio_hal_arch_no_port_write_pins(), and led_strip_switch().
|
static |
Interrupt service routine for Port port.
port | Number between 0 and 3. Port A: 0, Port B: 1, etc. |
Definition at line 52 of file gpio.c.
References GPIO_CLEAR_INTERRUPT, GPIO_CLEAR_POWER_UP_INTERRUPT, GPIO_GET_MASKED_INT_STATUS, GPIO_GET_POWER_UP_INT_STATUS, GPIO_PORT_TO_BASE, and int_status().